Datasheet AD7609 (Analog Devices) - 9

制造商Analog Devices
描述8-Channel Differential DAS with 18-Bit, Bipolar, Simultaneous Sampling ADC
页数 / 页37 / 9 — AD7609. Data Sheet. Limit at TMIN, TMAX. Parameter. Min. Typ. Max. Unit. …
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AD7609. Data Sheet. Limit at TMIN, TMAX. Parameter. Min. Typ. Max. Unit. Description

AD7609 Data Sheet Limit at TMIN, TMAX Parameter Min Typ Max Unit Description

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AD7609 Data Sheet Limit at TMIN, TMAX Parameter Min Typ Max Unit Description
t13 Delay from CS until DB[15:0] three-state disabled 19 ns VDRIVE above 4.75 V 24 ns VDRIVE above 3.3 V 30 ns VDRIVE above 2.7 V 37 ns VDRIVE above 2.3 V t 3 14 Data access time after RD falling edge 19 ns VDRIVE above 4.75 V 24 ns VDRIVE above 3.3 V 30 ns VDRIVE above 2.7 V 37 ns VDRIVE above 2.3 V t15 6 ns Data hold time after RD falling edge t16 6 ns CS to DB[15:0] hold time t17 22 ns Delay from CS rising edge to DB[15:0] three-state enabled SERIAL READ OPERATION fSCLK Frequency of serial read clock 20 MHz VDRIVE above 4.75 V 15 MHz VDRIVE above 3.3 V 12.5 MHz VDRIVE above 2.7 V 10 MHz VDRIVE above 2.3 V t18 Delay from CS until DOUTA/DOUTB three-state disabled/delay from CS until MSB valid 18 ns VDRIVE above 4.75 V 23 ns VDRIVE above 3.3 V 35 ns VDRIVE = 2.3 V to 2.7 V t 3 19 Data access time after SCLK rising edge 20 ns VDRIVE above 4.75 V 26 ns VDRIVE above 3.3 V 32 ns VDRIVE above 2.7 V 39 ns VDRIVE above 2.3 V t20 0.4 tSCLK ns SCLK low pulse width t21 0.4 tSCLK ns SCLK high pulse width t22 7 SCLK rising edge to DOUTA/DOUTB valid hold time t23 22 ns CS rising edge to DOUTA/DOUTB three-state enabled FRSTDATA OPERATION t24 Delay from CS falling edge until FRSTDATA three-state disabled 18 ns VDRIVE above 4.75 V 23 ns VDRIVE above 3.3 V 30 ns VDRIVE above 2.7 V 35 ns VDRIVE above 2.3 V t25 ns Delay from CS falling edge until FRSTDATA high, serial mode 18 ns VDRIVE above 4.75 V 23 ns VDRIVE above 3.3 V 30 ns VDRIVE above 2.7 V 35 ns VDRIVE above 2.3 V t26 Delay from RD falling edge to FRSTDATA high 19 ns VDRIVE above 4.75 V 23 ns VDRIVE above 3.3 V 30 ns VDRIVE above 2.7 V 35 ns VDRIVE above 2.3 V Rev. B | Page 8 of 36 Document Outline Features Applications Companion Products Functional Block Diagram Table of Contents Revision History General Description Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Converter Details Analog Input Analog Input Ranges Analog Input Impedance Analog Input Clamp Protection Analog Input Antialiasing Filter Track-and-Hold Amplifiers ADC Transfer Function Internal/External Reference External Reference Mode Internal Reference Mode Typical Connection Diagram Power-Down Modes Conversion Control Simultaneous Sampling on All Analog Input Channels Simultaneously Sampling Two Sets of Channels Digital Interface Parallel Interface (/PAR/SER SEL = 0) Serial Interface (/PAR/SER SEL = 1) Reading During Conversion Digital Filter Layout Guidelines Outline Dimensions Ordering Guide