Datasheet AD9484 (Analog Devices)

8-Bit, 500 MSPS, 1.8 V Analog-to-Digital Converter AD9484 FEATURES FUNCTIONAL BLOCK DIAGRAM SNR = 47 dBFS at f VREF PWDN AGND AVDD IN up to 250 MHz at 500 MSPS ENOB of 7.5 bits at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS) SFDR = 79 dBc at f REFERENCE AD9484 IN up to 250 MHz at 500 MSPS (−1.0 dBFS) Integrated input buffer CML DRVDD Excellent linearity DRGND VIN+ TRACK-AND-HOLD DNL = ±0.1 LSB typical VIN– ADC 8 OUTPUT 8 INL = ±0.1 LSB typical CORE STAGING D7± TO D0± LVDS LVDS at 500 MSPS (ANSI-644 levels) CLK+ CLOCK OR+ 1 GHz full power analog bandwidth CLK– MANAGEMENT OR– On-chip reference, no external decoupling required SERIAL PORT Low power dissipation DCO+ 670 mW at 500 MSPS—LVDS SDR output DCO–
1 -00 5
Programmable (nominal) input voltage range
61
SCLK/DFS SDIO CSB
09
1.18 V p-p to 1.6 V p-p, 1.5 V p-p nominal
Figure 1.
1.8 V analog and digital supply operation Selectable output data format (offset binary, twos complement, Gray code) Clock duty cycle stabilizer Integrated data capture clock APPLICATIONS Wireless and wired broadband communications Cable reverse path Communications test equipment Low cost digital oscilloscopes Satellite subsystems Power amplifier linearization GENERAL DESCRIPTION
The AD9484 is an 8-bit, monolithic, sampling analog-to-digital Fabricated on an advanced BiCMOS process, the AD9484 is availa- converter (ADC) optimized for high performance, low power, ble in a 56-lead LFCSP, and is specified over the industrial and ease of use. The part operates at up to a 500 MSPS conver- temperature range (−40°C to +85°C). This product is protected sion rate and is optimized for outstanding dynamic performance by a U.S. patent. in wideband carrier and broadband systems. All necessary
PRODUCT HIGHLIGHTS
functions, including a sample-and-hold and voltage reference, are included on the chip to provide a complete signal conversion 1. High Performance. solution. The VREF pin can be used to monitor the internal Maintains 47 dBFS SNR at 500 MSPS with a 250 MHz input. reference or provide an external voltage reference (external 2. Ease of Use. reference mode must be enabled through the SPI port). LVDS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and The ADC requires a 1.8 V analog voltage supply and a differen- sample-and-hold provide flexibility in system design. Use tial clock for full performance operation. The digital outputs are of a single 1.8 V supply simplifies system power supply design. LVDS (ANSI-644) compatible and support twos complement, 3. Serial Port Control. offset binary format, or Gray code. A data clock output is available Standard serial port interface supports various product for proper output data timing. functions, such as data formatting, power-down, gain adjust, and output test pattern generation.
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING VREF AD9484 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE