Datasheet AD9434 (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | 12-Bit, 370 MSPS/500 MSPS, 1.8 V Analog-to-Digital Converter |
| 页数 / 页 | 29 / 9 — AD9434. Data Sheet. ABSOLUTE MAXIMUM RATINGS Table 5. Parameter. Rating. … |
| 修订版 | B |
| 文件格式/大小 | PDF / 937 Kb |
| 文件语言 | 英语 |
AD9434. Data Sheet. ABSOLUTE MAXIMUM RATINGS Table 5. Parameter. Rating. THERMAL RESISTANCE. Table 6. Package Type. θJA. θJC. Unit
该数据表的模型线
文件文字版本
AD9434 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 5.
Stresses above those listed under Absolute Maximum Ratings
Parameter Rating
may cause permanent damage to the device. This is a stress Electrical rating only; functional operation of the device at these or any AVDD to AGND −0.3 V to +2.0 V other conditions above those indicated in the operational DRVDD to DRGND −0.3 V to +2.0 V section of this specification is not implied. Exposure to absolute AGND to DRGND −0.3 V to +0.3 V maximum rating conditions for extended periods may affect AVDD to DRVDD −2.0 V to +2.0 V device reliability. D0+/D0− Through D11+/D11− −0.3 V to DRVDD + 0.2 V
THERMAL RESISTANCE
to DRGND DCO+, DCO− to DRGND −0.3 V to DRVDD + 0.2 V The exposed paddle must be soldered to the ground plane for OR+, OR− to DRGND −0.3 V to DRVDD + 0.2 V the LFCSP package. Soldering the exposed paddle to the PCB CLK+ to AGND −0.3 V to AVDD + 0.2 V increases the reliability of the solder joints, maximizing the CLK− to AGND −0.3 V to AVDD + 0.2 V thermal capability of the package. VIN+ to AGND −0.3 V to AVDD + 0.4 V
Table 6.
VIN− to AGND −0.3 V to AVDD + 0.4 V
Package Type θJA θJC Unit
CML to AGND −0.3 V to AVDD + 0.2 V 56-Lead LFCSP_VQ (CP-56-5) 23.7 1.7 °C/W VREF to AGND −0.3 V to AVDD + 0.2 V SDIO to DRGND −0.3 V to DRVDD + 0.2 V Typical θJA and θJC are specified for a 4-layer board in still air. PDWN to AGND −0.3 V to DRVDD + 0.2 V Airflow increases heat dissipation, effectively reducing θJA. In CSB to AGND −0.3 V to DRVDD + 0.2 V addition, metal in direct contact with the package leads from SCLK/DFS to AGND −0.3 V to DRVDD + 0.2 V metal traces, through holes, ground, and power planes reduces Environmental the θJA. Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C
ESD CAUTION
Lead Temperature 300°C (Soldering, 10 sec) Junction Temperature 150°C Rev. B | Page 8 of 28 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input and Voltage Reference Differential Input Configurations Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) Timing VREF AD9434 Configuration Using the SPI Using the AD9434 to Replace the AD9230 Hardware Interface Configuration Without the SPI Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Outline Dimensions Ordering Guide
Stresses above those listed under Absolute Maximum Ratings
Parameter Rating
may cause permanent damage to the device. This is a stress Electrical rating only; functional operation of the device at these or any AVDD to AGND −0.3 V to +2.0 V other conditions above those indicated in the operational DRVDD to DRGND −0.3 V to +2.0 V section of this specification is not implied. Exposure to absolute AGND to DRGND −0.3 V to +0.3 V maximum rating conditions for extended periods may affect AVDD to DRVDD −2.0 V to +2.0 V device reliability. D0+/D0− Through D11+/D11− −0.3 V to DRVDD + 0.2 V
THERMAL RESISTANCE
to DRGND DCO+, DCO− to DRGND −0.3 V to DRVDD + 0.2 V The exposed paddle must be soldered to the ground plane for OR+, OR− to DRGND −0.3 V to DRVDD + 0.2 V the LFCSP package. Soldering the exposed paddle to the PCB CLK+ to AGND −0.3 V to AVDD + 0.2 V increases the reliability of the solder joints, maximizing the CLK− to AGND −0.3 V to AVDD + 0.2 V thermal capability of the package. VIN+ to AGND −0.3 V to AVDD + 0.4 V
Table 6.
VIN− to AGND −0.3 V to AVDD + 0.4 V
Package Type θJA θJC Unit
CML to AGND −0.3 V to AVDD + 0.2 V 56-Lead LFCSP_VQ (CP-56-5) 23.7 1.7 °C/W VREF to AGND −0.3 V to AVDD + 0.2 V SDIO to DRGND −0.3 V to DRVDD + 0.2 V Typical θJA and θJC are specified for a 4-layer board in still air. PDWN to AGND −0.3 V to DRVDD + 0.2 V Airflow increases heat dissipation, effectively reducing θJA. In CSB to AGND −0.3 V to DRVDD + 0.2 V addition, metal in direct contact with the package leads from SCLK/DFS to AGND −0.3 V to DRVDD + 0.2 V metal traces, through holes, ground, and power planes reduces Environmental the θJA. Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C
ESD CAUTION
Lead Temperature 300°C (Soldering, 10 sec) Junction Temperature 150°C Rev. B | Page 8 of 28 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input and Voltage Reference Differential Input Configurations Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) Timing VREF AD9434 Configuration Using the SPI Using the AD9434 to Replace the AD9230 Hardware Interface Configuration Without the SPI Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Outline Dimensions Ordering Guide