AD7608Data SheetLimit at TMIN, TMAXParameterMinTypMaxUnitDescription t27 Delay from RDE falling edge to FRSTDATA low A A 19 ns VDRIVE = 3.3 V to 5.25 V 24 ns VDRIVE = 2.3 V to 2.7 V t28 Delay from 16th SCLK falling edge to FRSTDATA low 17 ns VDRIVE = 3.3 V to 5.25 V 22 ns VDRIVE = 2.3 V to 2.7 V t29 24 ns Delay from CSE rising edge until FRSTDATA three-state enabled A A 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 2 The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <40 LSB performance matching between channel sets. 3 A buffer is used on the data output pins for these measurements, which is equivalent to a load of 20 pF on the output pins. Timing Diagramst5CONVST A/CONVST BtCYCLEt2CONVST A/CONVST Bt3tCONVt1BUSYt4CSt7tRESETRESET 002 08938- Figure 2.CONVST x Timing—Reading After a Conversion t5CONVST A/CONVST BtCYCLEt2CONVST A/CONVST Bt3tCONVt1BUSYt6CSt7tRESETRESET 003 08938- Figure 3. CONVST x Timing—Reading During a Conversion CSt9t8tt1110RDt16t13tt1417t15DATA:V1V1V2V2V8V8DB[15:0]INVALID[17:2][1:0][17:2][1:0][17:2][1:0]t26t27t29t24 004 FRSTDATA 08938- Figure 4. Parallel Mode Separate CSE and RDE Pulses A A A A Rev. A | Page 8 of 32 Document Outline Features Applications Companion Products Functional Block Diagram Table of Contents Revision History General Description Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Converter Details Analog Input Analog Input Ranges Analog Input Impedance Analog Input Clamp Protection Analog Input Antialiasing Filter Track-and-Hold Amplifiers ADC Transfer Function Internal/External Reference External Reference Mode Internal Reference Mode Typical Connection Diagram Power-Down Modes Conversion Control Simultaneous Sampling on All Analog Input Channels Simultaneously Sampling Two Sets of Channels Digital Interface Parallel Interface (/SER SEL = 0) Serial Interface (/SER SEL = 1) Reading During Conversion Digital Filter Layout Guidelines Outline Dimensions Ordering Guide