Datasheet AD7291 (Analog Devices) - 6

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Data Sheet AD7291 I2C TIMING SPECIFICATIONS
Guaranteed by initial characterization. All values were measured with the input filtering enabled. CB refers to the capacitive load on the bus line, with tR and tF measured between 0.3 × VDRIVE and 0.7 × VDRIVE (see Figure 2). VDD = 2.8 V to 3.6 V; VDRIVE = 1.65 V to 3.6 V; VREF = 2.5 V internal/external; TA = −40°C to +125°C, unless otherwise noted.
Table 3. Limit at TMIN, TMAX Parameter Conditions Min Typ Max Unit Description
f SCL Standard mode 100 kHz Serial clock frequency Fast mode 400 kHz t 1 Standard mode 4 µs tHIGH, SCL high time Fast mode 0.6 µs t 2 Standard mode 4.7 µs tLOW, SCL low time Fast mode 1.3 µs t 3 Standard mode 250 ns tSU;DAT, data setup time Fast mode 100 ns t 1 4 Standard mode 0 3.45 µs tHD;DAT, data hold time Fast mode 0 0.9 µs t 5 Standard mode 4.7 µs tSU;STA, setup time for a repeated start condition Fast mode 0.6 µs t 6 Standard mode 4 µs tHD;STA, hold time for a repeated start condition Fast mode 0.6 µs t 7 Standard mode 4.7 µs tBUF, bus-free time between a stop and a start condition Fast mode 1.3 µs t 8 Standard mode 4 µs tSU;STO, setup time for a stop condition Fast mode 0.6 µs t9 Standard mode 1000 ns tRDA, rise time of the SDA signal Fast mode 20 + 0.1 CB 300 ns t10 Standard mode 300 ns tFDA, fall time of the SDA signal Fast mode 20 + 0.1 CB 300 ns t11 Standard mode 1000 ns tRCL, rise time of the SCL signal Fast mode 20 + 0.1 CB 300 ns t11A Standard mode 1000 ns tRCL1, rise time of the SCL signal after a repeated Fast mode 20 + 0.1 CB 300 ns start condition and after an acknowledge bit t12 Standard mode 300 ns tFCL, fall time of the SCL signal Fast mode 20 + 0.1 CB 300 ns t SP Fast mode 0 50 ns Pulse width of the suppressed spike tPOWER-UP 6 ms Power-up and acquisition time 1 A device must provide a data hold time for SDA to bridge the undefined region of the SCL falling edge.
t11 t12 t2 t6 SCL t6 t4 t t 3 5 t8 t1 t10 t9 SDA t7 S P S P S = START CONDITION P = STOP CONDITION
002 08711- Figure 2. 2-Wire Serial Interface Timing Diagram Rev. C | Page 5 of 28 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS I2C TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY CIRCUIT INFORMATION CONVERTER OPERATION ANALOG INPUT ADC TRANSFER FUNCTION TEMPERATURE SENSOR OPERATION TEMPERATURE SENSOR AVERAGING Temperature Value Format VDRIVE THE INTERNAL OR EXTERNAL REFERENCE RESET INTERNAL REGISTER STRUCTURE ADDRESS POINTER REGISTER COMMAND REGISTER (0x00) Sample Delay and Bit Trial Delay VOLTAGE CONVERSION RESULT REGISTER (0x01) Temperature Value Format TSENSE CONVERSION RESULT REGISTER (0x02) TSENSE AVERAGE RESULT REGISTER (0X03) LIMIT REGISTERS (0X04 TO 0X1E) DATAHIGH Register DATALOW Register HYSTERESIS REGISTER ALERT STATUS REGISTER A AND ALERT STATUS REGISTER B (0x1F AND 0x20) I2C INTERFACE SERIAL BUS ADDRESS BYTE GENERAL I2C TIMING WRITING TO THE AD7291 WRITING TWO BYTES OF DATA TO A 16-BIT REGISTER WRITING TO MULTIPLE REGISTERS READING DATA FROM THE AD7291 READING TWO BYTES OF DATA FROM A 16-BIT REGISTER MODES OF OPERATION COMMAND MODE AUTOCYCLE MODE OUTLINE DIMENSIONS ORDERING GUIDE