Datasheet AD9644 (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | 14-Bit, 80 MSPS/155 MSPS, 1.8V Dual, Serial Output A/D Converter |
| 页数 / 页 | 45 / 5 — AD9644. Data Sheet. SPECIFICATIONS. ADC DC SPECIFICATIONS. Table 1. … |
| 修订版 | C |
| 文件格式/大小 | PDF / 1.5 Mb |
| 文件语言 | 英语 |
AD9644. Data Sheet. SPECIFICATIONS. ADC DC SPECIFICATIONS. Table 1. AD9644-80. AD9644-155. Parameter. Temperature Min. Typ. Max. Min. Unit
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AD9644 Data Sheet SPECIFICATIONS ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, DCS enabled, unless otherwise noted.
Table 1. AD9644-80 AD9644-155 Parameter Temperature Min Typ Max Min Typ Max Unit
RESOLUTION Full 14 14 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±2 ±10 ±2.2 ±11 mV Gain Error Full −7 −2.5 +1 −6 −1.5 +4 % FSR Differential Nonlinearity (DNL)1 Full ±0.55 ±0.55 LSB 25°C ±0.3 ±0.3 LSB Integral Nonlinearity (INL)1 Full ±1.1 ±1.25 LSB 25°C ±0.5 ±0.55 LSB MATCHING CHARACTERISTIC Offset Error Full −7 +1.5 +10 −6 +1.5 +9 mV Gain Error Full −1.5 +0.6 +2.75 −3.1 +0.75 +5 % FSR TEMPERATURE DRIFT Offset Error Full ±2 ±2 ppm/°C Gain Error Full ±35 ±144 ppm/°C INPUT REFERRED NOISE 25°C 0.7 0.7 LSB rms ANALOG INPUT Input Span Full 1.383 1.75 2.087 1.383 1.75 2.087 V p-p Input Capacitance2 Full 7 5 pF Input Resistance Full 20 20 kΩ VCM OUTPUT LEVEL Full 0.88 0.9 0.92 0.87 0.9 0.93 V POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Current IAVDD1 Full 175 190 226 242 mA IDRVDD1 Full 60 67 89 97 mA POWER CONSUMPTION Sine Wave Input1 Full 423 460 567 610 mW Standby Power3 Full 85 168 mW Power-Down Power Full 15 27 18 27 mW 1 Measured with a low input frequency, full-scale sine wave. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 3 Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND). Rev. C | Page 4 of 44 Document Outline Features Applications Functional Block Diagram Product Highlights Revision History General Description Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Channel/Chip Synchronization Power Dissipation and Standby Mode Digital Outputs JESD204A Transmit Top Level Description Initial Frame Synchronization Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing Built-In Self-Test (BIST) and Output Test Built-In Self-Test (BIST) Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Sync Control (Register 0x3A) Bits[7:3]—Open Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Buffer Enable JESD204A Quick Configure (Register 0x5E) Bits[7:3]—Reserved Bits[2:0]—Register Quick Configuration JESD204A Lane Assignment (Register 0x5F) Bits[7:4]—Reserved Bits[3:0]—JESD204A Serial Lane Control JESD204A Link Control Register 1 (Register 0x60) Bit 7—Reserved Bit 6—Serial Tail Bit Enable Bit 5—Serial Test Sample Enable Bit 4—Serial Lane Synchronization Enable Bits[3:2]—Serial Lane Alignment Sequence Mode Bit 1—Frame Alignment Character Insertion Disable Bit 0—Serial Transmit Link Powered Down JESD204A Link Control Register 2 (Register 0x61) Bits[7:6]—Local DSYNC Mode Bit 5—DSYNC Pin Input Inverted Bit 4—CMOS DSYNC Input Bit 3—Open Bit 2—Bypass 8b/10b Encoding Bit 1—Invert Transmit Bits Bit 0—Mirror Serial Output Bits JESD204A Link Control Register 3 (Register 0x62) Bit 7—Disable CHKSUM Bit 6—Open Bits[5:4]—Link Test Generation Input Selection Bit 3—Open Bits[2:0]—Link Test Generation Mode JESD204A Link Control Register 4 (Register 0x63) Bits[7:0]—Initial Lane Alignment Sequence Repeat Count JESD204A Device Identification Number (DID) (Register 0x64) Bits[7:0]—Serial Device Identification (DID) Number JESD204A Bank Identification Number (BID) (Register 0x65) Bits[7:4]—Open Bits[3:0]—Serial Bank Identification (DID) Number JESD204A Lane Identification Number (LID) for Lane 0 (Register 0x66) Bits[7:5]—Open Bits[4:0]—Serial Lane Identification (LID) Number for Lane 0. JESD204A Lane Identification Number (LID) for Lane 1 (Register 0x67) Bits[7:5]—Open Bits[4:0]—Serial Lane Identification (LID) Number for Lane 1. JESD204A Scrambler (SCR) and Lane Configuration Registers (Register 0x6E) Bit 7—Enable Serial Scrambler Mode Bits[6:1]—Open Bit[0]—Serial Lane Control. JESD204A Number of Octets Per Frame (F) (Register 0x6F—Read Only) Bits[7:0]—Number of Octets per Frame (F) JESD204A Number of Frames Per Multiframe (Register 0x70) Bits[7:5]—Reserved Bits[4:0]—Number of Frames per Multiframe (K). JESD204A Number of Converters Per Link (M) (Register 0x71) Bits[7:1]—Reserved Bit 0—Number of Converters per Link per Device (M). JESD204A ADC Resolution (N) and Control Bits Per Sample (CS) (Register 0x72) Bits[7:6]—Number of Control Bits per Sample (CS) Bit 5—Open Bits[4:0]—Converter Resolution (N) JESD204A Total Bits Per Sample (N’) (Register 0x73) Bits[7:5]—Open Bits[4:0]—Total Number of Bits per Sample (N’) JESD204A Samples Per Converter (S) Frame Cycle (Register 0x74) Bits[7:5]—Open Bits[4:0]—Samples per Converter Frame Cycle (S) JESD204A HD and CF Configuration (Register 0x75) Bit 7—Enable High Density Format (Read Only) Bits[6:5]—Reserved Bits[4:0]—Number of Control Words per Frame Clock Cycle per Link (CF) JESD204A Serial Reserved Field 1 (Register 0x76) Bits[7:0]—Serial Reserved Field 1 (RES1) JESD204A Serial Reserved Field 2 (Register 0x77) Bits[7:0]—Serial Reserved Field 2 (RES2) JESD204A Serial Checksum Value for Lane 0 (Register 0x78) Bits[7:0]—Serial Checksum Value for Lane 0 JESD204A Serial Checksum Value for Lane 1 (Register 0x79) Bits[7:0]—Serial Checksum Value for Lane 1 Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCMA and VCMB SPI Port Outline Dimensions Ordering Guide
AD9644 Data Sheet SPECIFICATIONS ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, DCS enabled, unless otherwise noted.
Table 1. AD9644-80 AD9644-155 Parameter Temperature Min Typ Max Min Typ Max Unit
RESOLUTION Full 14 14 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±2 ±10 ±2.2 ±11 mV Gain Error Full −7 −2.5 +1 −6 −1.5 +4 % FSR Differential Nonlinearity (DNL)1 Full ±0.55 ±0.55 LSB 25°C ±0.3 ±0.3 LSB Integral Nonlinearity (INL)1 Full ±1.1 ±1.25 LSB 25°C ±0.5 ±0.55 LSB MATCHING CHARACTERISTIC Offset Error Full −7 +1.5 +10 −6 +1.5 +9 mV Gain Error Full −1.5 +0.6 +2.75 −3.1 +0.75 +5 % FSR TEMPERATURE DRIFT Offset Error Full ±2 ±2 ppm/°C Gain Error Full ±35 ±144 ppm/°C INPUT REFERRED NOISE 25°C 0.7 0.7 LSB rms ANALOG INPUT Input Span Full 1.383 1.75 2.087 1.383 1.75 2.087 V p-p Input Capacitance2 Full 7 5 pF Input Resistance Full 20 20 kΩ VCM OUTPUT LEVEL Full 0.88 0.9 0.92 0.87 0.9 0.93 V POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Current IAVDD1 Full 175 190 226 242 mA IDRVDD1 Full 60 67 89 97 mA POWER CONSUMPTION Sine Wave Input1 Full 423 460 567 610 mW Standby Power3 Full 85 168 mW Power-Down Power Full 15 27 18 27 mW 1 Measured with a low input frequency, full-scale sine wave. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 3 Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND). Rev. C | Page 4 of 44 Document Outline Features Applications Functional Block Diagram Product Highlights Revision History General Description Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Channel/Chip Synchronization Power Dissipation and Standby Mode Digital Outputs JESD204A Transmit Top Level Description Initial Frame Synchronization Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing Built-In Self-Test (BIST) and Output Test Built-In Self-Test (BIST) Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Sync Control (Register 0x3A) Bits[7:3]—Open Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Buffer Enable JESD204A Quick Configure (Register 0x5E) Bits[7:3]—Reserved Bits[2:0]—Register Quick Configuration JESD204A Lane Assignment (Register 0x5F) Bits[7:4]—Reserved Bits[3:0]—JESD204A Serial Lane Control JESD204A Link Control Register 1 (Register 0x60) Bit 7—Reserved Bit 6—Serial Tail Bit Enable Bit 5—Serial Test Sample Enable Bit 4—Serial Lane Synchronization Enable Bits[3:2]—Serial Lane Alignment Sequence Mode Bit 1—Frame Alignment Character Insertion Disable Bit 0—Serial Transmit Link Powered Down JESD204A Link Control Register 2 (Register 0x61) Bits[7:6]—Local DSYNC Mode Bit 5—DSYNC Pin Input Inverted Bit 4—CMOS DSYNC Input Bit 3—Open Bit 2—Bypass 8b/10b Encoding Bit 1—Invert Transmit Bits Bit 0—Mirror Serial Output Bits JESD204A Link Control Register 3 (Register 0x62) Bit 7—Disable CHKSUM Bit 6—Open Bits[5:4]—Link Test Generation Input Selection Bit 3—Open Bits[2:0]—Link Test Generation Mode JESD204A Link Control Register 4 (Register 0x63) Bits[7:0]—Initial Lane Alignment Sequence Repeat Count JESD204A Device Identification Number (DID) (Register 0x64) Bits[7:0]—Serial Device Identification (DID) Number JESD204A Bank Identification Number (BID) (Register 0x65) Bits[7:4]—Open Bits[3:0]—Serial Bank Identification (DID) Number JESD204A Lane Identification Number (LID) for Lane 0 (Register 0x66) Bits[7:5]—Open Bits[4:0]—Serial Lane Identification (LID) Number for Lane 0. JESD204A Lane Identification Number (LID) for Lane 1 (Register 0x67) Bits[7:5]—Open Bits[4:0]—Serial Lane Identification (LID) Number for Lane 1. JESD204A Scrambler (SCR) and Lane Configuration Registers (Register 0x6E) Bit 7—Enable Serial Scrambler Mode Bits[6:1]—Open Bit[0]—Serial Lane Control. JESD204A Number of Octets Per Frame (F) (Register 0x6F—Read Only) Bits[7:0]—Number of Octets per Frame (F) JESD204A Number of Frames Per Multiframe (Register 0x70) Bits[7:5]—Reserved Bits[4:0]—Number of Frames per Multiframe (K). JESD204A Number of Converters Per Link (M) (Register 0x71) Bits[7:1]—Reserved Bit 0—Number of Converters per Link per Device (M). JESD204A ADC Resolution (N) and Control Bits Per Sample (CS) (Register 0x72) Bits[7:6]—Number of Control Bits per Sample (CS) Bit 5—Open Bits[4:0]—Converter Resolution (N) JESD204A Total Bits Per Sample (N’) (Register 0x73) Bits[7:5]—Open Bits[4:0]—Total Number of Bits per Sample (N’) JESD204A Samples Per Converter (S) Frame Cycle (Register 0x74) Bits[7:5]—Open Bits[4:0]—Samples per Converter Frame Cycle (S) JESD204A HD and CF Configuration (Register 0x75) Bit 7—Enable High Density Format (Read Only) Bits[6:5]—Reserved Bits[4:0]—Number of Control Words per Frame Clock Cycle per Link (CF) JESD204A Serial Reserved Field 1 (Register 0x76) Bits[7:0]—Serial Reserved Field 1 (RES1) JESD204A Serial Reserved Field 2 (Register 0x77) Bits[7:0]—Serial Reserved Field 2 (RES2) JESD204A Serial Checksum Value for Lane 0 (Register 0x78) Bits[7:0]—Serial Checksum Value for Lane 0 JESD204A Serial Checksum Value for Lane 1 (Register 0x79) Bits[7:0]—Serial Checksum Value for Lane 1 Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCMA and VCMB SPI Port Outline Dimensions Ordering Guide