Datasheet AD7606, AD7606-6, AD7606-4 (Analog Devices) - 3

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Data Sheet AD7606/AD7606-6/AD7606-4 GENERAL DESCRIPTION
The AD76061/AD7606-6/AD7606-4 are 16-bit, simultaneous The AD7606/AD7606-6/AD7606-4 operate from a single 5 V sampling, analog-to-digital data acquisition systems (DAS) with supply and can accommodate ±10 V and ±5 V true bipolar input eight, six, and four channels, respectively. Each part contains signals while sampling at throughput rates up to 200 kSPS for analog input clamp protection, a second-order antialiasing filter, al channels. The input clamp protection circuitry can tolerate a track-and-hold amplifier, a 16-bit charge redistribution successive voltages up to ±16.5 V. The AD7606 has 1 MΩ analog input approximation analog-to-digital converter (ADC), a flexible impedance regardless of sampling frequency. The single supply digital filter, a 2.5 V reference and reference buffer, and high operation, on-chip filtering, and high input impedance eliminate speed serial and paral el interfaces. the need for driver op amps and external bipolar supplies. The AD7606/AD7606-6/AD7606-4 antialiasing filter has a 3 dB cutoff frequency of 22 kHz and provides 40 dB antialias rejection when sampling at 200 kSPS. The flexible digital filter is pin driven, yields improvements in SNR, and reduces the 3 dB bandwidth. 1 Patent pending. Rev. C | Page 3 of 36 Document Outline Features Applications Functional Block Diagram Revision History General Description Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Converter Details Analog Input Analog Input Ranges Analog Input Impedance Analog Input Clamp Protection Analog Input Antialiasing Filter Track-and-Hold Amplifiers ADC Transfer Function Internal/External Reference Typical Connection Diagram Power-Down Modes Conversion Control Simultaneous Sampling on All Analog Input Channels Simultaneously Sampling Two Sets of Channels Digital Interface Parallel Interface (PAR/SER/BYTE SEL = 0) Parallel Byte (PAR/SER/BYTE SEL = 1, DB15 = 1) Serial Interface (PAR/SER/BYTE SEL = 1) Reading During Conversion Digital Filter Layout Guidelines Outline Dimensions Ordering Guide