Datasheet AD7606, AD7606-6, AD7606-4 (Analog Devices) - 7

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Data Sheet AD7606/AD7606-6/AD7606-4 TIMING SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, VREF = 2.5 V external reference/internal reference, TA = TMIN to TMAX, unless otherwise noted.1
Table 3. Limit at TMIN, TMAX Limit at TMIN, TMAX (0.1 × VDRIVE and (0.3 × VDRIVE and 0.9 × VDRIVE 0.7 × VDRIVE Logic Input Levels) Logic Input Levels) Parameter Min Typ Max Min Typ Max Unit Description
PARALLEL/SERIAL/BYTE MODE tCYCLE 1/throughput rate 5 5 µs Parallel mode, reading during or after conversion; or serial mode: VDRIVE = 3.3 V to 5.25 V, reading during a conversion using DOUTA and DOUTB lines 9.4 µs Serial mode reading after a conversion; VDRIVE = 2.7 V 9.7 10.7 µs Serial mode reading after a conversion; VDRIVE = 2.3 V, DOUTA and DOUTB lines t 2 CONV Conversion time 3.45 4 4.15 3.45 4 4.15 µs Oversampling off; AD7606 3 3 µs Oversampling off; AD7606-6 2 2 µs Oversampling off; AD7606-4 7.87 9.1 7.87 9.1 µs Oversampling by 2; AD7606 16.05 18.8 16.05 18.8 µs Oversampling by 4; AD7606 33 39 33 39 µs Oversampling by 8; AD7606 66 78 66 78 µs Oversampling by 16; AD7606 133 158 133 158 µs Oversampling by 32; AD7606 257 315 257 315 µs Oversampling by 64; AD7606 tWAKE-UP STANDBY 100 100 µs STBY rising edge to CONVST x rising edge; power-up time from standby mode tWAKE-UP SHUTDOWN Internal Reference 30 30 ms STBY rising edge to CONVST x rising edge; power-up time from shutdown mode External Reference 13 13 ms STBY rising edge to CONVST x rising edge; power-up time from shutdown mode tRESET 50 50 ns RESET high pulse width tOS_SETUP 20 20 ns BUSY to OS x pin setup time tOS_HOLD 20 20 ns BUSY to OS x pin hold time t1 40 45 ns CONVST x high to BUSY high t2 25 25 ns Minimum CONVST x low pulse t3 25 25 ns Minimum CONVST x high pulse t4 0 0 ns BUSY falling edge to CS falling edge setup time t 3 5 0.5 0.5 ms Maximum delay al owed between CONVST A, CONVST B rising edges t6 25 25 ns Maximum time between last CS rising edge and BUSY fal ing edge t7 25 25 ns Minimum delay between RESET low to CONVST x high PARALLEL/BYTE READ OPERATION t8 0 0 ns CS to RD setup time t9 0 0 ns CS to RD hold time t10 RD low pulse width 16 19 ns VDRIVE above 4.75 V 21 24 ns VDRIVE above 3.3 V 25 30 ns VDRIVE above 2.7 V 32 37 ns VDRIVE above 2.3 V t11 15 15 ns RD high pulse width t12 22 22 ns CS high pulse width (see Figure 5); CS and RD linked Rev. C | Page 7 of 36 Document Outline Features Applications Functional Block Diagram Revision History General Description Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Converter Details Analog Input Analog Input Ranges Analog Input Impedance Analog Input Clamp Protection Analog Input Antialiasing Filter Track-and-Hold Amplifiers ADC Transfer Function Internal/External Reference Typical Connection Diagram Power-Down Modes Conversion Control Simultaneous Sampling on All Analog Input Channels Simultaneously Sampling Two Sets of Channels Digital Interface Parallel Interface (PAR/SER/BYTE SEL = 0) Parallel Byte (PAR/SER/BYTE SEL = 1, DB15 = 1) Serial Interface (PAR/SER/BYTE SEL = 1) Reading During Conversion Digital Filter Layout Guidelines Outline Dimensions Ordering Guide