Datasheet AD9261 (Analog Devices) - 3
| 制造商 | Analog Devices |
| 描述 | 16-Bit, 10 MHz Bandwidth, 30 MSPS to 160 MSPS Continuous Time Sigma-Delta ADC |
| 页数 / 页 | 29 / 3 — AD9261. TABLE OF CONTENTS. REVISION HISTORY. 4/10—Revision 0: Initial … |
| 文件格式/大小 | PDF / 624 Kb |
| 文件语言 | 英语 |
AD9261. TABLE OF CONTENTS. REVISION HISTORY. 4/10—Revision 0: Initial Version
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AD9261 TABLE OF CONTENTS
Features .. 1 Typical Performance Characteristics ..9 Applications ... 1 Equivalent Circuits ... 13 Functional Block Diagram .. 1 Theory of Operation .. 14 General Description ... 1 Analog Input Considerations ... 14 Product Highlights ... 1 Clock Input Considerations .. 16 Revision History ... 2 Power Dissipation and Standby Mode .. 18 Specifications ... 3 Digital Engine ... 19 DC Specifications ... 3 Digital Outputs ... 21 AC Specifications .. 4 Timing ... 21 Digital Decimation Filtering Characteristics .. 4 Serial Port Interface (SPI) .. 23 Digital Specifications ... 5 Configuration Using the SPI ... 23 Switching Specifications .. 6 Hardware Interface ... 24 Absolute Maximum Ratings .. 7 Memory Map .. 25 Thermal Resistance .. 7 Memory Map Definitions ... 25 ESD Caution .. 7 Outline Dimensions ... 27 Pin Configuration and Function Descriptions ... 8 Ordering Guide .. 27
REVISION HISTORY 4/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 28 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Decimation Filtering Characteristics Digital Specifications Switching Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Direct Clocking Internal PLL Clock Distribution External PLL Control PLL Autoband Select Jitter Considerations Power Dissipation and Standby Mode Digital Engine Bandwidth Selection Decimation Filters Sample Rate Converter Cascaded Filter Responses Digital Outputs Digital Output Format Overrange (OR) Condition Timing Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Memory Map Memory Map Definitions Outline Dimensions Ordering Guide
AD9261 TABLE OF CONTENTS
Features .. 1 Typical Performance Characteristics ..9 Applications ... 1 Equivalent Circuits ... 13 Functional Block Diagram .. 1 Theory of Operation .. 14 General Description ... 1 Analog Input Considerations ... 14 Product Highlights ... 1 Clock Input Considerations .. 16 Revision History ... 2 Power Dissipation and Standby Mode .. 18 Specifications ... 3 Digital Engine ... 19 DC Specifications ... 3 Digital Outputs ... 21 AC Specifications .. 4 Timing ... 21 Digital Decimation Filtering Characteristics .. 4 Serial Port Interface (SPI) .. 23 Digital Specifications ... 5 Configuration Using the SPI ... 23 Switching Specifications .. 6 Hardware Interface ... 24 Absolute Maximum Ratings .. 7 Memory Map .. 25 Thermal Resistance .. 7 Memory Map Definitions ... 25 ESD Caution .. 7 Outline Dimensions ... 27 Pin Configuration and Function Descriptions ... 8 Ordering Guide .. 27
REVISION HISTORY 4/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 28 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Decimation Filtering Characteristics Digital Specifications Switching Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Direct Clocking Internal PLL Clock Distribution External PLL Control PLL Autoband Select Jitter Considerations Power Dissipation and Standby Mode Digital Engine Bandwidth Selection Decimation Filters Sample Rate Converter Cascaded Filter Responses Digital Outputs Digital Output Format Overrange (OR) Condition Timing Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Memory Map Memory Map Definitions Outline Dimensions Ordering Guide