Datasheet AD9269 (Analog Devices)

16-Bit, 20/40/65/80 MSPS, 1.8 V Dual Analog-to-Digital Converter Data Sheet AD9269 FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V analog supply operation AVDD GND SDIO SCLK CSB 1.8 V to 3.3 V output supply Integrated quadrature error correction (QEC) SPI AD9269 SNR ORA R 77.6 dBFS at 9.7 MHz input FFE VIN+A PROGRAMMING DATA D15A S U O 71 dBFS at 200 MHz input ADC T B VIN–A CM U D0A SFDR TP 93 dBc at 9.7 MHz input OU DCOA VREF 80 dBc at 200 MHz input QUADRATURE TION SENSE Low power ERROR DRVDD OP CORRECTION X REF 44 mW per channel at 20 MSPS VCM U SELECT M ORB 100 mW per channel at 80 MSPS RBIAS R Differential input with 700 MHz bandwidth FFE VIN–B D15B S U ADC O On-chip voltage reference and sample-and-hold circuit T B VIN+B CM U D0B 2 V p-p differential analog input TP OU DNL = −0.5/+1.1 LSB DCOB Serial port control options DIVIDE DUTY CYCLE MODE Offset binary, gray code, or twos complement data format 1 TO 6 STABILIZER CONTROLS
001
Optional clock duty cycle stabilizer (DCS) CLK+ CLK– SYNC DCS PDWN DFS OEB Integer 1-to-6 input clock divider
08538- Figure 1.
Data output multiplex option Built-in selectable digital test pattern generation PRODUCT HIGHLIGHTS Energy-saving power-down modes
1. The AD9269 operates from a single 1.8 V analog power
Data clock output (DCO) with programmable clock and
supply and features a separate digital output driver supply
data alignment
to accommodate 1.8 V to 3.3 V logic families. 2. The patented sample-and-hold circuit maintains excel ent
APPLICATIONS
performance for input frequencies up to 200 MHz and is
Communications
designed for low cost, low power, and ease of use.
Diversity radio systems
3. An optional SPI selectable dc correction and quadrature
Multimode digital receivers
error correction (QEC) feature corrects for dc offset, gain,
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
and phase mismatches between the two channels.
I/Q demodulation systems
4. A standard serial port interface (SPI) supports various
Smart antenna systems
product features and functions, such as data output format-
Battery-powered instruments
ting, internal clock divider, power-down, DCO/data timing
Handheld scope meters
and offset adjustments, and voltage reference modes.
Portable medical imaging
5. The AD9269 is packaged in a 64-lead RoHS-compliant
Ultrasound
LFCSP that is pin compatible with the AD9268 16-bit
Radar/LIDAR
ADC, the AD9258 14-bit ADC, the AD9251 14-bit ADC the AD9231 12-bit ADC, the AD6659 12-bit baseband diversity receiver, and the AD9204 10-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS.
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Document Outline Features Applications Functional Block Diagram Product Highlights Revision History General Description Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9269-80 AD9269-65 AD9269-40 AD9269-20 Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Single-Ended Input Configuration Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) Built-In Self-Test (BIST) and Output Test Built-In Self-Test (BIST) Output Test Modes Channel/Chip Synchronization DC and Quadrature Error Correction (QEC) LO Leakage (DC) Correction QEC and DC Correction Range Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Sync Control (Register 0x100) Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable USR2 (Register 0x101) Bit 7—Enable OEB (Pin 47) Bits [6:4]—Open Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 1—Open Bit 0—Disable SDIO Pull-Down QEC Control 0 (Register 0x110) Bits[7:6]—Open Bits[5:3]—Freeze DC/Freeze Phase/Freeze Gain Bits[2:0]—DC Enable/Phase Enable/Gain Enable QEC Control 1 (Register 0x111) Bits[7:3]—Open Bit 2—Force DC Bit 1—Force Phase Bit 0—Force Gain QEC Gain Bandwidth Control (Register 0x112) Bits[7:5]—Open Bits[4:0]—KEXP_GAIN QEC Phase Bandwidth Control (Register 0x113) Bits[7:5]—Open Bits[4:0]—KEXP_PHASE QEC DC Bandwidth Control (Register 0x114) Bits[7:5]—Open Bits[4:0]—KEXP_DC QEC Initial Gain 0, QEC Initial Gain 1 (Register 0x116 and Register 0x117) Bits[14:0]—Initial Gain QEC Initial Phase 0, QEC Initial Phase 1 (Register 0x118 and Register 0x119) Bits[12:0]—Initial Phase QEC Initial DC I 0, QEC Initial DC I 1 (Register 0x11A and Register 0x11B) Bits[13:0]—Initial DC I QEC Initial DC Q 0, QEC Initial DC Q 1 (Register 0x11C and Register 0x11D) Bits[13:0]—Initial DC Q Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide