Datasheet AD7195 (Analog Devices) - 10

Data Sheet AD7195 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 2 1 /RDY K K K C L L L UT N CS SC MC MC DI DO NC SYN 32 31 30 29 28 27 26 25 ACX2 1 24 DVDD ACX2 2 23 AVDD ACX1 3 22 DGND AD7195 ACX1 4 21 AGND AV TOP VIEW DD 5 20 BPDSW (Not to Scale) AGND 6 19 NC NC 7 18 REFIN(–) AINCOM 8 17 REFIN(+) 9 10 11 12 13 14 15 16 1 2 3 4 N N NC NC NC NC N N AI AI AI AI NOTES
005
1. NC = NO CONNECT.
1-
2. CONNECT EXPOSED PAD TO AGND.
77 08 Figure 5.Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 ACX2 Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac excited bridge applications. In ac mode, ACX2 toggles in anti-phase with ACX1. If the ACX bit equals zero (ac excitation turned off), the ACX2 output remains low. When toggling, it is guaranteed to be nonoverlapping with ACX1. The nonoverlap interval between ACX1 and ACX2 is 1/(master clock) which is equal to 200 ns when a 4.92 MHz clock is used. 2 ACX2 Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac excited bridge applications. This output is the inverse of ACX2. If the ACX bit equals zero (ac excitation turned off), the ACX2 output remains high. 3 ACX1 Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac excited bridge applications. When ACX1 is high, the bridge excitation is taken as normal and when ACX1 is low, the bridge excitation is reversed (chopped). If the Bit ACX equals zero (ac excitation turned off), the ACX1 output remains high. 4 ACX1 Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac excited bridge applications. This output is the inverse of ACX1. When ACX1 is low, the bridge excitation is taken as normal and when ACX1 is high, the bridge excitation is reversed (chopped). If the ACX bit equals zero (ac excitation turned off), the ACX1 output remains low. 5 AVDD Analog Supply Voltage, 4.75 V to 5.25 V. AVDD is independent of DVDD. 6 AGND Analog Ground Reference Point. 7 NC No Connect. This pin should be tied to AGND. 8 AINCOM Analog inputs AIN1 to AIN4 are referenced to this input when configured for pseudo differential operation. 9 AIN1 Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with AIN2 or as a pseudo differential input when used with AINCOM. 10 AIN2 Analog Input. This pin can be configured as the negative input of a fully differential input pair when used with AIN1 or as a pseudo differential input when used with AINCOM. 11 NC No Connect. This pin should be tied to AGND. 12 NC No Connect. This pin should be tied to AGND. 13 NC No Connect. This pin should be tied to AGND. 14 NC No Connect. This pin should be tied to AGND. 15 AIN3 Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with AIN4 or as a pseudo differential input when used with AINCOM. 16 AIN4 Analog Input. This pin can be configured as the negative input of a fully differential input pair when used with AIN3 or as a pseudo differential input when used with AINCOM. 17 REFIN(+) Positive Reference Input. An external reference can be applied between REFIN(+) and REFIN(−). REFIN(+) can lie anywhere between AVDD and AGND + 1 V. The nominal reference voltage, (REFIN(+) − REFIN(−)), is AVDD, but the part functions with a reference from 1 V to AVDD. 18 REFIN(−) Negative Reference Input. This reference input can lie anywhere between AGND and AVDD − 1 V. 19 NC No Connect. This pin should be tied to AGND. Rev. A | Page 9 of 44 Document Outline FEATURES INTERFACE APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Circuit and Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS RMS NOISE AND RESOLUTION SINC4 CHOP DISABLED SINC3 CHOP DISABLED SINC4 CHOP ENABLED SINC3 CHOP ENABLED ON-CHIP REGISTERS COMMUNICATIONS REGISTER STATUS REGISTER MODE REGISTER CONFIGURATION REGISTER DATA REGISTER ID REGISTER GPOCON REGISTER OFFSET REGISTER FULL-SCALE REGISTER ADC CIRCUIT INFORMATION OVERVIEW Analog Inputs Multiplexer PGA Reference Detect Burnout Currents Σ-Δ ADC and Filter AC Excitation Serial Interface Clock Temperature Sensor Calibration ANALOG INPUT CHANNEL PGA REFERENCE REFERENCE DETECT BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING BURNOUT CURRENTS AC EXCITATION CHANNEL SEQUENCER Single Conversion Mode Continuous Conversion Mode Continuous Read RESET SYSTEM SYNCHRONIZATION CLOCK ENABLE PARITY TEMPERATURE SENSOR BRIDGE POWER-DOWN SWITCH CALIBRATION DIGITAL FILTER SINC4 FILTER (CHOP DISABLED) Sinc4 Output Data Rate/Settling Time Sinc4 Zero Latency Sinc4 50 Hz/60 Hz Rejection SINC3 FILTER (CHOP DISABLED) Sinc3 Output Data Rate and Settling Time Sinc3 Zero Latency Sinc3 50 Hz/60 Hz Rejection CHOP ENABLED (SINC4 FILTER) Output Data Rate and Settling Time (Sinc4 Chop Enabled) 50 Hz/60 Hz Rejection (Sinc4 Chop Enabled) CHOP ENABLED (SINC3 FILTER) Output Data Rate and Settling Time (Sinc3 Chop Enabled) 50 Hz/60 Hz Rejection (Sinc3 Chop Enabled) SUMMARY OF FILTER OPTIONS GROUNDING AND LAYOUT APPLICATIONS INFORMATION WEIGH SCALES OUTLINE DIMENSIONS ORDERING GUIDE