Datasheet AD9649 (Analog Devices) - 4

Data Sheet AD9649 GENERAL DESCRIPTION
The AD9649 is a monolithic, single channel 1.8 V supply, 14-bit, pseudorandom patterns, along with custom user-defined test 20/40/65/80 MSPS analog-to-digital converter (ADC). It features patterns entered via the serial port interface (SPI). a high performance sample-and-hold circuit and an on-chip volt- A differential clock input with optional 1, 2, or 4 divide ratios age reference. controls al internal conversion cycles. The product uses multistage differential pipeline architecture The digital output data is presented in offset binary, gray code, or with output error correction logic to provide 14-bit accuracy at twos complement format. A data output clock (DCO) is provided 80 MSPS data rates and to guarantee no missing codes over the to ensure proper latch timing with receiving logic. Both 1.8 V and full operating temperature range. 3.3 V CMOS levels are supported. The ADC contains several features designed to maximize flexibility The AD9649 is available in a 32-lead RoHS-compliant LFCSP and and minimize system cost, such as programmable clock and data is specified over the industrial temperature range (−40°C to alignment and programmable digital test pattern generation. The +85°C). available digital test patterns include built-in deterministic and Rev. B | Page 3 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9649-80 AD9649-65 AD9649-40 AD9649-20 EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE OPEN LOCATIONS DEFAULT VALUES Logic Levels Transfer Register Map MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS USR2 (Register 0x101) Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 0—Disable SDIO Pull-Down APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations Encode Clock VCM RBIAS Reference Decoupling SPI Port Soft Reset OUTLINE DIMENSIONS ORDERING GUIDE