Datasheet AD9609 (Analog Devices) - 2

AD9609* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS TOOLS AND SIMULATIONS
View a parametric search of comparable parts. • Visual Analog • AD9609 IBIS Model
EVALUATION KITS
• AD9609 Evaluation Board
REFERENCE MATERIALS Technical Articles DOCUMENTATION
• Improve The Design Of Your Passive Wideband ADC
Application Notes
Front-End Network • AN-1142: Techniques for High Speed ADC PCB Layout • MS-2210: Designing Power Supplies for High Speed ADC • AN-586: LVDS Outputs for High Speed A/D Converters • AN-742: Frequency Domain Response of Switched-
DESIGN RESOURCES
Capacitor ADCs • AD9609 Material Declaration • AN-807: Multicarrier WCDMA Feasibility • PCN-PDN Information • AN-808: Multicarrier CDMA2000 Feasibility • Quality And Reliability • AN-812: MicroController-Based Serial Port Interface (SPI) • Symbols and Footprints Boot Circuit • AN-827: A Resonant Approach to Interfacing Amplifiers to
DISCUSSIONS
Switched-Capacitor ADCs View all AD9609 EngineerZone Discussions. • AN-878: High Speed ADC SPI Control Software • AN-935: Designing an ADC Transformer-Coupled Front
SAMPLE AND BUY
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Data Sheet
• AD9609: 10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8
TECHNICAL SUPPORT
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User Guides
number. • Evaluating the AD9266/AD9649/AD9629/AD9609 Analog- to-Digital Converters
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9609-80 AD9609-65 AD9609-40 AD9609-20 EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE OPEN LOCATIONS DEFAULT VALUES Logic Levels Transfer Register Map MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS USR2 (Register 0x101) Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 0—Disable SDIO Pull-Down APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations Encode Clock VCM RBIAS Reference Decoupling SPI Port Soft Reset OUTLINE DIMENSIONS ORDERING GUIDE