Datasheet AD9255 (Analog Devices) - 4

Data Sheet AD9255 GENERAL DESCRIPTION
The AD9255 is a 14-bit, 125 MSPS analog-to-digital converter A differential clock input controls al internal conversion cycles. A (ADC). The AD9255 is designed to support communications duty cycle stabilizer provides the means to compensate for vari- applications where high performance combined with low cost, ations in the ADC clock duty cycle, allowing the converters to smal size, and versatility is desired. maintain excellent performance over a wide range of input The ADC core features a multistage, differential pipelined clock duty cycles. An integrated voltage reference eases design architecture with integrated output error correction logic to considerations. provide 14-bit accuracy at 125 MSPS data rates and guarantees The ADC output data format is either parallel 1.8 V CMOS or no missing codes over the full operating temperature range. LVDS (DDR). A data output clock is provided to ensure proper The ADC features a wide bandwidth differential sample-and- latch timing with receiving logic. hold analog input amplifier supporting a variety of user-selectable Programming for setup and control is accomplished using a 3-wire input ranges. It is suitable for multiplexed systems that switch SPI-compatible serial interface. Flexible power-down options full-scale voltage levels in successive channels and for sampling allow significant power savings, when desired. An optional on- single-channel inputs at frequencies well beyond the Nyquist rate. chip dither function is available to improve SFDR performance Combined with power and cost savings over previously available with low power analog input signals. ADCs, the AD9255 is suitable for applications in communications, The AD9255 is available in a Pb-free, 48-lead LFCSP and is instrumentation, and medical imaging. specified over the industrial temperature range of −40°C to +85°C. Rev. C | Page 3 of 44 Document Outline Features Applications Product Highlights Functional Block Diagram Table of Contents Revision History General Description Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Dither Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Clock Duty Cycle Input Clock Divider Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) Built-In Self-Test (BIST) and Output Test Built-In Self-Test (BIST) Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Transfer Register Map Memory Map Register Table Memory Map Register Descriptions Sync Control (Register 0x100) Applications Information Design Guidelines Power and Ground Recommendations LVDS Operation Exposed Paddle Thermal Heat Slug Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide