Datasheet AD9231 (Analog Devices)

制造商Analog Devices
描述12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter
页数 / 页37 / 1 — 12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,. 1.8 V Dual Analog-to-Digital …
修订版B
文件格式/大小PDF / 970 Kb
文件语言英语

12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,. 1.8 V Dual Analog-to-Digital Converter. Data Sheet. AD9231. FEATURES

Datasheet AD9231 Analog Devices, 修订版: B

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12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter Data Sheet AD9231 FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V analog supply operation AVDD GND SDIO SCLK CSB 1.8 V to 3.3 V output supply SNR SPI ORA 71.3 dBFS at 9.7 MHz input R 69.0 dBFS at 200 MHz input FFE VIN+A PROGRAMMING DATA D11A S U O SFDR ADC T B VIN–A CM U D0A 93 dBc at 9.7 MHz input TP OU 83 dBc at 200 MHz input DCOA VREF Low power TION SENSE DRVDD 32 mW per channel at 20 MSPS OP AD9231 X VCM REF U 71 mW per channel at 80 MSPS SELECT M ORB RBIAS R Differential input with 700 MHz bandwidth FFE D11B On-chip voltage reference and sample-and-hold circuit VIN–B S U ADC O T B 2 V p-p differential analog input VIN+B CM U D0B TP DNL = ±0.40 LSB OU DCOB Serial port control options Offset binary, gray code, or twos complement data format DIVIDE DUTY CYCLE MODE 1 TO 8 STABILIZER CONTROLS Optional clock duty cycle stabilizer
001
Integer 1-to-8 input clock divider CLK+ CLK– SYNC DCS PDWN DFS OEB
08121-
Data output multiplex option
Figure 1.
Built-in selectable digital test pattern generation Energy-saving power-down modes PRODUCT HIGHLIGHTS Data clock out with programmable clock and data alignment
1. The AD9231 operates from a single 1.8 V analog power supply and features a separate digital output driver supply
APPLICATIONS
to accommodate 1.8 V to 3.3 V logic families.
Communications
2. The patented sample-and-hold circuit maintains excellent
Diversity radio systems
performance for input frequencies up to 200 MHz and is
Multimode digital receivers
designed for low cost, low power, and ease of use.
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
3. A standard serial port interface supports various product
I/Q demodulation systems
features and functions, such as data output formatting,
Smart antenna systems
internal clock divider, power-down, DCO/DATA timing
Battery-powered instruments
and offset adjustments, and voltage reference modes.
Hand held scope meters
4. The AD9231 is packaged in a 64-lead RoHS compliant
Portable medical imaging
LFCSP that is pin compatible with the AD9268 16-bit
Ultrasound
ADC, the AD9258 14-bit ADC, the AD9251 14-bit ADC,
Radar/LIDAR
and the AD9204 10-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS.
Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2009–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9231-80 AD9231-65 AD9231-40 AD9231-20 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE OPEN LOCATIONS DEFAULT VALUES Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Sync Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable Bit 7—Enable OEB Pin 47 Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 0—Disable SDIO Pull-Down APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE