Datasheet AD9231 (Analog Devices) - 2

AD9231* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS TOOLS AND SIMULATIONS
View a parametric search of comparable parts. • Visual Analog • AD9231 IBIS Models
EVALUATION KITS
• AD9204/AD9231/AD9251 S-Parameter Data • AD9231 Evaluation Board
REFERENCE MATERIALS DOCUMENTATION Product Selection Guide Application Notes
• RF Source Booklet • AN-1142: Techniques for High Speed ADC PCB Layout
Technical Articles
• AN-742: Frequency Domain Response of Switched- • Improve The Design Of Your Passive Wideband ADC Capacitor ADCs Front-End Network • AN-812: MicroController-Based Serial Port Interface (SPI) • MS-2210: Designing Power Supplies for High Speed ADC Boot Circuit • AN-827: A Resonant Approach to Interfacing Amplifiers to
DESIGN RESOURCES
Switched-Capacitor ADCs • AD9231 Material Declaration • AN-877: Interfacing to High Speed ADCs via SPI • PCN-PDN Information • AN-878: High Speed ADC SPI Control Software • Quality And Reliability • AN-905: Visual Analog Converter Evaluation Tool Version 1.0 User Manual • Symbols and Footprints • AN-935: Designing an ADC Transformer-Coupled Front End
DISCUSSIONS Data Sheet
View all AD9231 EngineerZone Discussions. • AD9231: 12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter Data Sheet
SAMPLE AND BUY User Guides
Visit the product page to see pricing options. • UG-003: Evaluating the AD9650/AD9268/AD9258/ AD9251/AD9231/AD9204 Analog-to-Digital Converters
TECHNICAL SUPPORT
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DOCUMENT FEEDBACK
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9231-80 AD9231-65 AD9231-40 AD9231-20 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE OPEN LOCATIONS DEFAULT VALUES Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Sync Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable Bit 7—Enable OEB Pin 47 Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 0—Disable SDIO Pull-Down APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE