Datasheet AD9231 (Analog Devices) - 10

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Data Sheet AD9231 ABSOLUTE MAXIMUM RATINGS Table 6. THERMAL CHARACTERISTICS Parameter Rating
The exposed paddle is the only ground connection for the chip. AVDD to AGND −0.3 V to +2.0 V The exposed paddle must be soldered to the AGND plane of the DRVDD to AGND −0.3 V to +3.9 V user’s circuit board. Soldering the exposed paddle to the user’s VIN+A, VIN+B, VIN−A, VIN−B to AGND −0.3 V to AVDD + 0.2 V board also increases the reliability of the solder joints and CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V maximizes the thermal capability of the package. SYNC to AGND −0.3 V to DRVDD + 0.3 V VREF to AGND −0.3 V to AVDD + 0.2 V
Table 7. Thermal Resistance
SENSE to AGND −0.3 V to AVDD + 0.2 V
Airflow
VCM to AGND −0.3 V to AVDD + 0.2 V
Velocity Package Type 1, 2 θ 1, 3 θ 1, 4 Unit
RBIAS to AGND −0.3 V to AVDD + 0.2 V
(m/sec) θJA JC JB
CSB to AGND −0.3 V to DRVDD + 0.3 V 64-Lead LFCSP 0 23 2.0 °C/W 9 mm × 9 mm SCLK/DFS to AGND −0.3 V to DRVDD + 0.3 V 1.0 20 12 °C/W (CP-64-4) SDIO/DCS to AGND −0.3 V to DRVDD + 0.3 V 2.5 18 °C/W OEB to AGND −0.3 V to DRVDD + 0.3 V 1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. PDWN to AGND −0.3 V to DRVDD + 0.3 V 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 D0A/D0B through D11A/D11B to AGND −0.3 V to DRVDD + 0.3 V Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). DCOA/DCOB to AGND −0.3 V to DRVDD + 0.3 V Operating Temperature Range (Ambient) −40°C to +85°C Typical θJA is specified for a 4-layer PCB with a solid ground Maximum Junction Temperature Under Bias 150°C plane. As shown in Table 7, airflow improves heat dissipation, Storage Temperature Range (Ambient) −65°C to +150°C which reduces θJA. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and Stresses at or above those listed under Absolute Maximum power planes, reduces the θJA. Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these
ESD CAUTION
or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 9 of 36 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9231-80 AD9231-65 AD9231-40 AD9231-20 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE OPEN LOCATIONS DEFAULT VALUES Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Sync Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable Bit 7—Enable OEB Pin 47 Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 0—Disable SDIO Pull-Down APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE