Datasheet AD9267 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | 10 MHz Bandwidth, 640 MSPS Dual Continuous Time Sigma-Delta Modulator |
| 页数 / 页 | 25 / 8 — AD9267. ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating. THERMAL … |
| 文件格式/大小 | PDF / 562 Kb |
| 文件语言 | 英语 |
AD9267. ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating. THERMAL RESISTANCE. Table 6. Thermal Resistance. Package Type. JA Unit
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AD9267 ABSOLUTE MAXIMUM RATINGS Table 5.
Stresses above those listed under Absolute Maximum Ratings
Parameter Rating
may cause permanent damage to the device. This is a stress Electrical rating only; functional operation of the device at these or any AVDD to AGND −0.3 V to +2.0 V other conditions above those indicated in the operational DVDD to DGND −0.3 V to +2.0 V section of this specification is not implied. Exposure to absolute DRVDD to DGND −0.3 V to +3.9 V maximum rating conditions for extended periods may affect AGND to DGND −0.3 V to +0.3 V device reliability. AVDD to DRVDD −3.9 V to +2.0 V
THERMAL RESISTANCE
CVDD to CGND −0.3 V to +2.0 V The exposed paddle must be soldered to the ground plane for CGND to DGND −0.3 V to +0.3 V the LFCSP package. Soldering the exposed paddle to the PCB D0±A to D3±A to DGND −0.3 V to +2.0 V increases the reliability of the solder joints, maximizing the D0±B to D3±B to DGND −0.3 V to +2.0 V thermal capability of the package. DCO± to DGND −0.3 V to +2.0 V OR±A, OR±B to DGND −0.3 V to +2.0 V Typical θJA and θJC are specified for a 4-layer board in still air. PDWNA to DGND −0.3 V to +3.9 V Airflow increases heat dissipation, effectively reducing θJA. In PDWNB to DGND −0.3 V to +3.9 V addition, metal in direct contact with the package leads from PLLMULTx to DGND −0.3 V to +3.9 V metal traces, through holes, ground, and power planes reduces SDIO to DGND −0.3 V to +3.9 V the θJA. CSB to AGND −0.3 V to +3.9 V
Table 6. Thermal Resistance
SCLK to AGND −0.3 V to +3.9 V
Package Type θ
VIN±A, VIN±B to AGND −0.3 V to +2.5 V
JA Unit
64-Lead LFCSP (CP-64-4) 22 °C/W CLK+, CLK− to CGND −0.3 V to +2.0 V Environmental Storage Temperature Range −65°C to +125°C
ESD CAUTION
Operating Temperature Range −40°C to +85°C Lead Temperature (Soldering, 10 sec) 300°C Junction Temperature 150°C Rev. 0 | Page 7 of 24 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Direct Clocking Internal PLL Clock Distribution External PLL Control PLL Autoband Select Power Dissipation and Standby Mode Digital Outputs Digital Output Format Overrange (OR) Condition Timing Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Applications Information Filtering Requirement Memory Map Memory Map Definitions Outline Dimensions Ordering Guide
Stresses above those listed under Absolute Maximum Ratings
Parameter Rating
may cause permanent damage to the device. This is a stress Electrical rating only; functional operation of the device at these or any AVDD to AGND −0.3 V to +2.0 V other conditions above those indicated in the operational DVDD to DGND −0.3 V to +2.0 V section of this specification is not implied. Exposure to absolute DRVDD to DGND −0.3 V to +3.9 V maximum rating conditions for extended periods may affect AGND to DGND −0.3 V to +0.3 V device reliability. AVDD to DRVDD −3.9 V to +2.0 V
THERMAL RESISTANCE
CVDD to CGND −0.3 V to +2.0 V The exposed paddle must be soldered to the ground plane for CGND to DGND −0.3 V to +0.3 V the LFCSP package. Soldering the exposed paddle to the PCB D0±A to D3±A to DGND −0.3 V to +2.0 V increases the reliability of the solder joints, maximizing the D0±B to D3±B to DGND −0.3 V to +2.0 V thermal capability of the package. DCO± to DGND −0.3 V to +2.0 V OR±A, OR±B to DGND −0.3 V to +2.0 V Typical θJA and θJC are specified for a 4-layer board in still air. PDWNA to DGND −0.3 V to +3.9 V Airflow increases heat dissipation, effectively reducing θJA. In PDWNB to DGND −0.3 V to +3.9 V addition, metal in direct contact with the package leads from PLLMULTx to DGND −0.3 V to +3.9 V metal traces, through holes, ground, and power planes reduces SDIO to DGND −0.3 V to +3.9 V the θJA. CSB to AGND −0.3 V to +3.9 V
Table 6. Thermal Resistance
SCLK to AGND −0.3 V to +3.9 V
Package Type θ
VIN±A, VIN±B to AGND −0.3 V to +2.5 V
JA Unit
64-Lead LFCSP (CP-64-4) 22 °C/W CLK+, CLK− to CGND −0.3 V to +2.0 V Environmental Storage Temperature Range −65°C to +125°C
ESD CAUTION
Operating Temperature Range −40°C to +85°C Lead Temperature (Soldering, 10 sec) 300°C Junction Temperature 150°C Rev. 0 | Page 7 of 24 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Direct Clocking Internal PLL Clock Distribution External PLL Control PLL Autoband Select Power Dissipation and Standby Mode Digital Outputs Digital Output Format Overrange (OR) Condition Timing Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Applications Information Filtering Requirement Memory Map Memory Map Definitions Outline Dimensions Ordering Guide