Datasheet AD9204 (Analog Devices) - 4

Data Sheet AD9204 GENERAL DESCRIPTION
The AD9204 is a monolithic, dual-channel, 1.8 V supply, 10-bit, A differential clock input controls al internal conversion cycles. 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter An optional duty cycle stabilizer (DCS) compensates for wide (ADC). It features a high performance sample-and-hold circuit variations in the clock duty cycle while maintaining excel ent and on-chip voltage reference. overal ADC performance. The product uses multistage differential pipeline architecture The digital output data is presented in offset binary, gray code, or with output error correction logic to provide 10-bit accuracy at twos complement format. A data output clock (DCO) is provided 80 MSPS data rates and to guarantee no missing codes over the for each ADC channel to ensure proper latch timing with receiving ful operating temperature range. logic. Both 1.8 V and 3.3 V CMOS levels are supported and output The ADC contains several features designed to maximize data can be multiplexed onto a single output bus. flexibility and minimize system cost, such as programmable The AD9204 is available in a 64-lead RoHS compliant LFCSP clock and data alignment and programmable digital test pattern and is specified over the industrial temperature range (−40°C generation. The available digital test patterns include built-in to +85°C). deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). Rev. A | Page 3 of 36 Document Outline Features Applications Functional Block Diagram Product Highlights Revision History General Description Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9204-80 AD9204-65 AD9204-40 AD9204-20 Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Single-Ended Input Configuration Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) Built-In Self-Test (BIST) and Output Test Built-In Self-Test (BIST) Output Test Modes Channel/Chip Synchronization Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers Memory Map Register Descriptions Sync Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable USR2 (Register 0x101) Bit 7—Enable OEB Pin 47 Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 0—Disable SDIO Pull-Down Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide