Datasheet AD9204 (Analog Devices) - 5

AD9204 Data Sheet SPECIFICATIONS DC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted.
Table 1. AD9204-20/AD9204-40 AD9204-65 AD9204-80 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION Full 10 10 10 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±0.1 ±0.70 ±0.1 ±0.50 ±0.1 ±0.70 % FSR Gain Error1 Full +1.8 +1.8 +1.8 % FSR Differential Nonlinearity (DNL)2 Full ±0.30 ±0.30 ±0.30 LSB 25°C ±0.075 ±0.15 ±0.11 LSB Integral Nonlinearity (INL)2 Full ±0.60 ±0.60 ±0.60 LSB 25°C ±0.15 ±0.25 ±0.25 LSB MATCHING CHARACTERISTICS Offset Error 25°C ±0.0 ±0.75 ±0.0 ±0.75 ±0.0 ±0.75 % FSR Gain Error1 25°C ±0.3 ±0.3 ±0.3 % FSR TEMPERATURE DRIFT Offset Error Full ±2 ±2 ±2 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Full 0.981 0.993 1.005 0.981 0.993 1.005 0.981 0.993 1.005 V Load Regulation Error at 1.0 mA Full 2 2 2 mV INPUT REFERRED NOISE VREF = 1.0 V 25°C 0.06 0.08 0.08 LSB rms ANALOG INPUT Input Span, VREF = 1.0 V Full 2 2 2 V p-p Input Capacitance3 Full 6 6 6 pF Input Common-Mode Voltage Full 0.9 0.9 0.9 V Input Common-Mode Range Full 0.5 1.3 0.5 1.3 0.5 1.3 V REFERENCE INPUT RESISTANCE Full 7.5 7.5 7.5 kΩ POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 3.6 1.7 3.6 1.7 3.6 V Supply Current IAVDD2 Full 33.5/46.4 35.8/49.6 61.1 64.8 70.3 75.2 mA IDRVDD2 (1.8 V) Full 2.6/4.4 6.5 8.0 mA IDRVDD2 (3.3 V) Full 5.0/8.3 12.4 15.3 mA POWER CONSUMPTION DC Input Full 59.5/82.1 108 125 mW Sine Wave Input2 (DRVDD = 1.8 V) Full 64.9/91.4 69.5/97.7 121.7 128.5 141 150 mW Sine Wave Input2 (DRVDD = 3.3 V) Full 76.7/111 150.8 177 mW Standby Power4 Full 37/37 37 37 mW Power-Down Power Full 2.2 2.2 2.2 mW 1 Measured with a 1.0 V external reference. 2 Measured with a 10 MHz input frequency at rated sample rate, ful -scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 4 Standby power is measured with a dc input, the CLK active. Rev. A | Page 4 of 36 Document Outline Features Applications Functional Block Diagram Product Highlights Revision History General Description Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9204-80 AD9204-65 AD9204-40 AD9204-20 Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Single-Ended Input Configuration Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) Built-In Self-Test (BIST) and Output Test Built-In Self-Test (BIST) Output Test Modes Channel/Chip Synchronization Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers Memory Map Register Descriptions Sync Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable USR2 (Register 0x101) Bit 7—Enable OEB Pin 47 Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 0—Disable SDIO Pull-Down Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide