Datasheet AD7780 (Analog Devices) - 4

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AD7780 SPECIFICATIONS
AVDD = 2.7 V to 5.25 V, VREF = AVDD, DVDD = 2.7 V to 5.25 V, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted.1
Table 2. Parameter Min Typ Max Unit Test Conditions/Comments
ADC CHANNEL Output Update Rate (fADC) 10 Hz FILTER = 1, settling time = 3/fADC 16.7 Hz FILTER = 0, settling time = 2/fADC No Missing Codes2 24 Bits Resolution Peak-to-Peak See Table 7 and Table 8 RMS Noise See Table 7 and Table 8 Integral Nonlinearity ±6 ppm of FSR Offset Error ±6 μV Gain = 128 with FILTER = 1 ±200 μV Gain = 1 with FILTER = 1 ±1 μV Gain = 128 with FILTER = 0 ±2 μV Gain = 1 with FILTER = 0 Offset Error Drift vs. Temperature ±10 nV/°C Gain = 128 ±150 nV/°C Gain = 1 with FILTER = 1 ±10 nV/°C Gain = 1 with FILTER = 0 Full-Scale Error ±0.25 % of FS Gain Drift vs. Temperature ±2 ppm/°C Power Supply Rejection 100 dB Gain = 128, FILTER = 1, AIN = 7.81 mV 120 dB Gain = 128, FILTER = 0, AIN = 7.81 mV Normal-Mode Rejection2 50 Hz, 60 Hz 63 75 dB 50 Hz ± 1 Hz, 60 Hz ± 1 Hz, fADC = 16.7 Hz 50 Hz, 60 Hz 72 90 dB 50 Hz ± 1 Hz, 60 Hz ± 1 Hz, fADC = 10 Hz Common-Mode Rejection DC 90 dB Gain = 1, AIN = 1 V 90 dB Gain = 128, AIN = 7.81 mV 50 Hz, 60 Hz 110 dB 50 Hz ± 1 Hz, 60 Hz ± 1 Hz ANALOG INPUTS Differential Input Voltage Range ±VREF/gain V VREF = REFIN(+) − REFIN(−), gain = 1 or 128 Absolute AIN Voltage Limits2 GND + 100 mV AVDD − 100 mV V Gain = 1 GND + 450 mV AVDD − 1.1 V Gain = 128, FILTER = 0 GND + 1.1 AVDD − 1.1 V Gain = 128, FILTER = 1, AVDD ≤ 3.6 V GND + 1.5 AVDD − 1.5 V Gain = 128, FILTER = 1, AVDD > 3.6 V Average Input Current ±1 nA Gain = 1 ±250 pA typ Gain = 128 Average Input Current Drift ±3 pA/°C REFERENCE External REFIN Voltage AVDD V REFIN = REFIN(+) − REFIN(−) Reference Voltage Range2 0.5 AVDD V Absolute REFIN Voltage Limits2 GND − 30 mV AVDD + 30 mV V Average Reference Input Current 400 nA/V Average Reference Input Current Drift ±0.15 nA/V/°C Normal-Mode Rejection Same as for analog inputs Common-Mode Rejection 110 dB BRIDGE POWER-DOWN SWITCH (BPDSW) Controlled via the PDRST pin RON 9 Ω Allowable Current2 30 mA Continuous current INTERNAL CLOCK Frequency 64 − 3% 64 + 3% kHz Duty Cycle 50:50 % Rev. A | Page 3 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Circuit and Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT NOISE AND RESOLUTION THEORY OF OPERATION FILTER, DATA RATE, AND SETTLING TIME GAIN POWER-DOWN/RESET () ANALOG INPUT CHANNEL BIPOLAR CONFIGURATION DATA OUTPUT CODING REFERENCE BRIDGE POWER-DOWN SWITCH DIGITAL INTERFACE APPLICATIONS INFORMATION WEIGH SCALES PERFORMANCE IN A WEIGH SCALE SYSTEM EMI RECOMMENDATIONS GROUNDING AND LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE