Datasheet AD7356 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | Differential Input, Dual, Simultaneous Sampling, 5 MSPS, 12-Bit, SAR ADC |
| 页数 / 页 | 21 / 6 — Data Sheet. AD7356. TIMING SPECIFICATIONS. Table 3. Parameter. Limit at … |
| 修订版 | B |
| 文件格式/大小 | PDF / 615 Kb |
| 文件语言 | 英语 |
Data Sheet. AD7356. TIMING SPECIFICATIONS. Table 3. Parameter. Limit at TMIN, TMAX. Unit. Description
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Data Sheet AD7356 TIMING SPECIFICATIONS
V 1 DD = 2.5 V ± 10%, VDRIVE = 2.25 V to 3.6 V, internal reference = 2.048 V, TA = TMAX to TMIN , unless otherwise noted.
Table 3. Parameter Limit at TMIN, TMAX Unit Description
fSCLK 50 kHz min 80 MHz max tCONVERT t2 + 13 × tSCLK ns max tSCLK = 1/fSCLK tQUIET 5 ns min Minimum time between end of serial read and next falling edge of CS t2 5 ns min CS to SCLK setup time t 2 3 6 ns max Delay from CS until SDATAA and SDATAB are three-state disabled t 2, 3 4 Data access time after SCLK falling edge 12.5 ns max 1.8 V ≤ VDRIVE < 2.25 V 11 ns max 2.25 V ≤ VDRIVE < 2.75 V 9.5 ns max 2.75 V ≤ VDRIVE < 3.3 V 9 ns max 3.3 V ≤ VDRIVE ≤ 3.6 V t5 5 ns min SCLK low pulse width t6 5 ns min SCLK high pulse width t 2 7 3.5 ns min SCLK to data valid hold time t 2 8 9.5 ns max CS rising edge to SDATAA, SDATAB high impedance t9 5 ns min CS rising edge to falling edge pulse width t 2 10 4.5 ns min SCLK falling edge to SDATAA, SDATAB high impedance 9.5 ns max SCLK falling edge to SDATAA, SDATAB high impedance 1 Temperature ranges are as fol ows: Y Grade: −40°C to +125°C; B Grade: −40°C to +85°C. 2 Specified with a load capacitance of 10 pF on SDATAA and SDATAB. 3 The time required for the output to cross 0.4 V or 2.4 V. Rev. B | Page 5 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ANALOG INPUT STRUCTURE ANALOG INPUTS DRIVING DIFFERENTIAL INPUTS Differential Amplifier Op Amp Pair VOLTAGE REFERENCE ADC TRANSFER FUNCTION MODES OF OPERATION NORMAL MODE PARTIAL POWER-DOWN MODE FULL POWER-DOWN MODE POWER-UP TIMES POWER vs. THROUGHPUT RATE SERIAL INTERFACE APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING THE AD7356 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
V 1 DD = 2.5 V ± 10%, VDRIVE = 2.25 V to 3.6 V, internal reference = 2.048 V, TA = TMAX to TMIN , unless otherwise noted.
Table 3. Parameter Limit at TMIN, TMAX Unit Description
fSCLK 50 kHz min 80 MHz max tCONVERT t2 + 13 × tSCLK ns max tSCLK = 1/fSCLK tQUIET 5 ns min Minimum time between end of serial read and next falling edge of CS t2 5 ns min CS to SCLK setup time t 2 3 6 ns max Delay from CS until SDATAA and SDATAB are three-state disabled t 2, 3 4 Data access time after SCLK falling edge 12.5 ns max 1.8 V ≤ VDRIVE < 2.25 V 11 ns max 2.25 V ≤ VDRIVE < 2.75 V 9.5 ns max 2.75 V ≤ VDRIVE < 3.3 V 9 ns max 3.3 V ≤ VDRIVE ≤ 3.6 V t5 5 ns min SCLK low pulse width t6 5 ns min SCLK high pulse width t 2 7 3.5 ns min SCLK to data valid hold time t 2 8 9.5 ns max CS rising edge to SDATAA, SDATAB high impedance t9 5 ns min CS rising edge to falling edge pulse width t 2 10 4.5 ns min SCLK falling edge to SDATAA, SDATAB high impedance 9.5 ns max SCLK falling edge to SDATAA, SDATAB high impedance 1 Temperature ranges are as fol ows: Y Grade: −40°C to +125°C; B Grade: −40°C to +85°C. 2 Specified with a load capacitance of 10 pF on SDATAA and SDATAB. 3 The time required for the output to cross 0.4 V or 2.4 V. Rev. B | Page 5 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ANALOG INPUT STRUCTURE ANALOG INPUTS DRIVING DIFFERENTIAL INPUTS Differential Amplifier Op Amp Pair VOLTAGE REFERENCE ADC TRANSFER FUNCTION MODES OF OPERATION NORMAL MODE PARTIAL POWER-DOWN MODE FULL POWER-DOWN MODE POWER-UP TIMES POWER vs. THROUGHPUT RATE SERIAL INTERFACE APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING THE AD7356 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE