Datasheet AD7190 (Analog Devices)
| 制造商 | Analog Devices |
| 描述 | 4.8 kHz Ultralow Noise 24-Bit Sigma-Delta ADC with PGA |
| 页数 / 页 | 41 / 1 — 4.8 kHz Ultralow Noise 24-Bit. Sigma-Delta ADC with PGA. Data Sheet. … |
| 修订版 | C |
| 文件格式/大小 | PDF / 689 Kb |
| 文件语言 | 英语 |
4.8 kHz Ultralow Noise 24-Bit. Sigma-Delta ADC with PGA. Data Sheet. AD7190. FEATURES. Temperature measurement
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4.8 kHz Ultralow Noise 24-Bit Sigma-Delta ADC with PGA Data Sheet AD7190 FEATURES Temperature measurement RMS noise: 8.5 nV @ 4.7 Hz (gain = 128) Chromatography 16 noise free bits @ 2.4 kHz (gain = 128) PLC/DCS analog input modules Up to 22.5 noise free bits (gain = 1) Data acquisition Offset drift: 5 nV/°C Medical and scientific instrumentation Gain drift: 1 ppm/°C GENERAL DESCRIPTION Specified drift over time
The AD7190 is a low noise, complete analog front end for high
2 differential/4 pseudo differential input channels
precision measurement applications. It contains a low noise,
Automatic channel sequencer
24-bit sigma-delta (∑-Δ) analog-to-digital converter (ADC).
Programmable gain (1 to 128)
The on-chip low noise gain stage means that signals of small
Output data rate: 4.7 Hz to 4.8 kHz
amplitude can be interfaced directly to the ADC.
Internal or external clock Simultaneous 50 Hz/60 Hz rejection
The device can be configured to have two differential inputs or
4 general-purpose digital outputs
four pseudo differential inputs. The on-chip channel sequencer
Power supply
allows several channels to be enabled, and the AD7190
AVDD: 4.75 V to 5.25 V
sequentially converts on each enabled channel. This simplifies
DVDD: 2.7 V to 5.25 V
communication with the part. The on-chip 4.92 MHz clock can
Current: 6 mA
be used as the clock source to the ADC or, alternatively, an
Temperature range: –40°C to +105°C
external clock or crystal can be used. The output data rate from
Interface
the part can be varied from 4.7 Hz to 4.8 kHz.
3-wire serial
The device has two digital filter options. The choice of filter
SPI, QSPI™, MICROWIRE™, and DSP compatible
affects the rms noise/noise-free resolution at the programmed
Schmitt trigger on SCLK
output data rate, the settling time, and the 50 Hz/60 Hz
Qualified for automotive applications
rejection. For applications that require all conversions to be
APPLICATIONS
settled, the AD7190 includes a zero latency feature.
Weigh scales
The part operates with 5 V analog power supply and a digital
Strain gauge transducers
power supply from 2.7 V to 5.25 V. It consumes a current of
Pressure measurement
6 mA. It is housed in a 24-lead TSSOP package.
FUNCTIONAL BLOCK DIAGRAM AGND AV DV DD DD DGND REFIN1(+) REFIN1(–) REFERENCE AD7190 DETECT AIN1 AIN2 AIN3 SERIAL DOUT/RDY AIN4 INTERFACE AINCOM MUX Σ-∆ PGA AND DIN ADC CONTROL SCLK LOGIC CS SYNC TEMP P3 SENSOR BPDSW P2 CLOCK CIRCUITRY AGND
01 0 0-
MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+)
64 07 Figure 1.
Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2008–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Characteristics Circuit and Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics RMS Noise and Resolution Sinc4 Chop Disabled Sinc3 Chop Disabled Sinc4 Chop Enabled Sinc3 Chop Enabled On-Chip Registers Communications Register Status Register Mode Register Configuration Register Data Register ID Register GPOCON Register Offset Register Full-Scale Register ADC Circuit Information Overview Filter, Output Data Rate, Settling Time Chop Disabled Chop Enabled 50 Hz/60 Hz Rejection Zero Latency Channel Sequencer Digital Interface Single Conversion Mode Continuous Conversion Mode Continuous Read Circuit Description Analog Input Channel PGA Bipolar/Unipolar Configuration Data Output Coding Clock Burnout Currents Reference Reference Detect Reset System Synchronization Temperature Sensor Bridge Power-Down Switch Logic Outputs Enable Parity Calibration Grounding and Layout Applications Information Weigh Scales Outline Dimensions Ordering Guide Automotive Products
The AD7190 is a low noise, complete analog front end for high
2 differential/4 pseudo differential input channels
precision measurement applications. It contains a low noise,
Automatic channel sequencer
24-bit sigma-delta (∑-Δ) analog-to-digital converter (ADC).
Programmable gain (1 to 128)
The on-chip low noise gain stage means that signals of small
Output data rate: 4.7 Hz to 4.8 kHz
amplitude can be interfaced directly to the ADC.
Internal or external clock Simultaneous 50 Hz/60 Hz rejection
The device can be configured to have two differential inputs or
4 general-purpose digital outputs
four pseudo differential inputs. The on-chip channel sequencer
Power supply
allows several channels to be enabled, and the AD7190
AVDD: 4.75 V to 5.25 V
sequentially converts on each enabled channel. This simplifies
DVDD: 2.7 V to 5.25 V
communication with the part. The on-chip 4.92 MHz clock can
Current: 6 mA
be used as the clock source to the ADC or, alternatively, an
Temperature range: –40°C to +105°C
external clock or crystal can be used. The output data rate from
Interface
the part can be varied from 4.7 Hz to 4.8 kHz.
3-wire serial
The device has two digital filter options. The choice of filter
SPI, QSPI™, MICROWIRE™, and DSP compatible
affects the rms noise/noise-free resolution at the programmed
Schmitt trigger on SCLK
output data rate, the settling time, and the 50 Hz/60 Hz
Qualified for automotive applications
rejection. For applications that require all conversions to be
APPLICATIONS
settled, the AD7190 includes a zero latency feature.
Weigh scales
The part operates with 5 V analog power supply and a digital
Strain gauge transducers
power supply from 2.7 V to 5.25 V. It consumes a current of
Pressure measurement
6 mA. It is housed in a 24-lead TSSOP package.
FUNCTIONAL BLOCK DIAGRAM AGND AV DV DD DD DGND REFIN1(+) REFIN1(–) REFERENCE AD7190 DETECT AIN1 AIN2 AIN3 SERIAL DOUT/RDY AIN4 INTERFACE AINCOM MUX Σ-∆ PGA AND DIN ADC CONTROL SCLK LOGIC CS SYNC TEMP P3 SENSOR BPDSW P2 CLOCK CIRCUITRY AGND
01 0 0-
MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+)
64 07 Figure 1.
Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2008–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Characteristics Circuit and Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics RMS Noise and Resolution Sinc4 Chop Disabled Sinc3 Chop Disabled Sinc4 Chop Enabled Sinc3 Chop Enabled On-Chip Registers Communications Register Status Register Mode Register Configuration Register Data Register ID Register GPOCON Register Offset Register Full-Scale Register ADC Circuit Information Overview Filter, Output Data Rate, Settling Time Chop Disabled Chop Enabled 50 Hz/60 Hz Rejection Zero Latency Channel Sequencer Digital Interface Single Conversion Mode Continuous Conversion Mode Continuous Read Circuit Description Analog Input Channel PGA Bipolar/Unipolar Configuration Data Output Coding Clock Burnout Currents Reference Reference Detect Reset System Synchronization Temperature Sensor Bridge Power-Down Switch Logic Outputs Enable Parity Calibration Grounding and Layout Applications Information Weigh Scales Outline Dimensions Ordering Guide Automotive Products