Datasheet AD7262 (Analog Devices) - 7

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AD7262 Data Sheet TIMING SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, CA_CBVCC = CC_CDVCC = 2.7 V to 5.25 V, VREF = 2.5 V internal/external; TA = TMIN to TMAX, unless otherwise noted.1
Table 2. Limit at TMIN, TMAX Parameter 2.7 V ≤ VDRIVE ≤ 3.6 V 4.75 V ≤ VDRIVE ≤ 5.25 V Unit Description
fSCLK 200 200 kHz min 40 40 MHz max AD7262 2 32 32 MHz typ AD72622 20 20 MHz max AD7262-5 tCONVERT 19 × tSCLK 19 × tSCLK ns max tSCLK = 1/fSCLK 475 475 ns max AD7262 950 950 ns max AD7262-5 tQUIET 13 13 ns min Minimum time between end of serial read/bus relinquish and next falling edge of CS t2 10 10 ns min CS to SCLK setup time t 3 3 15 15 ns max Delay from 19th SCLK falling edge until DOUTA and DOUTB are three-state disabled t4 29 23 ns max Data access time after SCLK falling edge t5 15 13 ns min SCLK to data valid hold time t6 0.4 × tSCLK 0.4 × tSCLK ns min SCLK high pulse width t7 0.4 × tSCLK 0.4 × tSCLK ns min SCLK low pulse width t8 13 13 ns min CS rising edge to falling edge pulse width t9 13 13 ns max CS rising edge to DOUTA, DOUTB, high impedance/bus relinquish t10 5 5 ns min SCLK falling edge to DOUTA, DOUTB, high impedance 35 35 ns max SCLK falling edge to DOUTA, DOUTB, high impedance t11 2 2 μs min Minimum CAL pin high time t12 2 2 μs min Minimum time between the CAL pin high and the CS falling edge t13 3 3 ns min DIN setup time prior to SCLK falling edge t14 3 3 ns min DIN hold time after SCLK falling edge tPOWER-UP 240 240 μs max Internal reference, with a 1 μF decoupling capacitor 15 15 μs max With an external reference, 10 μs typical 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of AVCC) and timed from a voltage level of 1.6 V. Al timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the Terminology section. 2 See the Serial Interface section. 3 The time required for the output to cross 0.4 V or 2.4 V.
TIMING DIAGRAM CS t8 t2 t6 SCLK 1 2 3 4 5 18 19 20 21 29 30 31 t7 t t 9 t3 t 5 4 tQUIET D DB11 DB10 DB9 DB1 OUTA A A A A DB0A THREE-STATE THREE- STATE D DB11 DB10 DB9 DB1 OUTB B B B B DB0B
002
THREE-STATE THREE- STATE
07606- Figure 2. Serial Interface Timing Diagram Rev. B | Page 6 of 32 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION COMPARATORS OPERATION ANALOG INPUTS Transfer Function VDRIVE REFERENCE TYPICAL CONNECTION DIAGRAMS Comparator Application Details APPLICATION DETAILS MODES OF OPERATION PIN-DRIVEN MODE GAIN SELECTION POWER-DOWN MODES Power-Up Conditions CONTROL REGISTER ON-CHIP REGISTERS Addressing the On-Chip Registers Writing to a Register Reading from a Register SERIAL INTERFACE CALIBRATION INTERNAL OFFSET CALIBRATION ADJUSTING THE OFFSET CALIBRATION REGISTERS SYSTEM GAIN CALIBRATION MICROPROCESSOR INTERFACING AD7262/AD7262-5 TO ADSP-BF531 APPLICATION HINTS GROUNDING AND LAYOUT PCB DESIGN GUIDELINES FOR LFCSP OUTLINE DIMENSIONS ORDERING GUIDE