Datasheet AD9230-11 (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | 11-Bit, 200 MSPS, 1.8 V Analog-to-Digital Converter |
| 页数 / 页 | 29 / 5 — AD9230-11. AC SPECIFICATIONS. Table 2. Parameter2. Temp. Min. Typ. Max. … |
| 文件格式/大小 | PDF / 665 Kb |
| 文件语言 | 英语 |
AD9230-11. AC SPECIFICATIONS. Table 2. Parameter2. Temp. Min. Typ. Max. Unit
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AD9230-11 AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.1
Table 2. Parameter2 Temp Min Typ Max Unit
SNR fIN = 10 MHz 25°C 62.4 62.9 dB Full 62.2 dB fIN = 70 MHz 25°C 62.2 62.5 dB Full 62.0 dB fIN = 170 MHz 25°C 61.8 dB SINAD fIN = 10 MHz 25°C 62.3 62.8 dB Full 62.1 dB fIN = 70 MHz 25°C 62.0 62.3 dB Full 61.8 dB fIN = 170 MHz 25°C 61.5 dB EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz 25°C 10.3 Bits fIN = 70 MHz 25°C 10.2 Bits fIN = 170 MHz 25°C 10.1 Bits WORST HARMONIC (SECOND OR THIRD) fIN = 10 MHz 25°C −86 −77 dBc Full −77 dBc fIN = 70 MHz 25°C −79 −77 dBc Full −76 dBc fIN = 170 MHz 25°C −76 dBc WORST OTHER (SFDR EXCLUDING SECOND AND THIRD) fIN = 10 MHz 25°C −88 −84 dBc Full −79 dBc fIN = 70 MHz 25°C −84 −82 dBc Full −81 dBc fIN = 170 MHz 25°C −82 dBc ANALOG INPUT BANDWIDTH 25°C 700 MHz 1 All ac specifications tested by driving CLK+ and CLK− differentially. 2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were completed. Rev. 0 | Page 4 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING RBIAS CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS TRANSFER REGISTER MAP OUTLINE DIMENSIONS ORDERING GUIDE
AD9230-11 AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.1
Table 2. Parameter2 Temp Min Typ Max Unit
SNR fIN = 10 MHz 25°C 62.4 62.9 dB Full 62.2 dB fIN = 70 MHz 25°C 62.2 62.5 dB Full 62.0 dB fIN = 170 MHz 25°C 61.8 dB SINAD fIN = 10 MHz 25°C 62.3 62.8 dB Full 62.1 dB fIN = 70 MHz 25°C 62.0 62.3 dB Full 61.8 dB fIN = 170 MHz 25°C 61.5 dB EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz 25°C 10.3 Bits fIN = 70 MHz 25°C 10.2 Bits fIN = 170 MHz 25°C 10.1 Bits WORST HARMONIC (SECOND OR THIRD) fIN = 10 MHz 25°C −86 −77 dBc Full −77 dBc fIN = 70 MHz 25°C −79 −77 dBc Full −76 dBc fIN = 170 MHz 25°C −76 dBc WORST OTHER (SFDR EXCLUDING SECOND AND THIRD) fIN = 10 MHz 25°C −88 −84 dBc Full −79 dBc fIN = 70 MHz 25°C −84 −82 dBc Full −81 dBc fIN = 170 MHz 25°C −82 dBc ANALOG INPUT BANDWIDTH 25°C 700 MHz 1 All ac specifications tested by driving CLK+ and CLK− differentially. 2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were completed. Rev. 0 | Page 4 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING RBIAS CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS TRANSFER REGISTER MAP OUTLINE DIMENSIONS ORDERING GUIDE