Datasheet AD7991, AD7995, AD7999 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | 4-Channel, 8-Bit ADC with I2C Compatible Interface in 8-Lead SOT-23 |
| 页数 / 页 | 28 / 7 — AD7991/AD7995/AD7999. AD79991. Table 4. A. Version2 Y. Version. … |
| 修订版 | C |
| 文件格式/大小 | PDF / 615 Kb |
| 文件语言 | 英语 |
AD7991/AD7995/AD7999. AD79991. Table 4. A. Version2 Y. Version. Parameter. Min Typ Max. Min Typ. Max. Unit. Test Conditions/Comments
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AD7991/AD7995/AD7999 AD79991
The temperature range for the Y version is −40°C to +125°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V, VREF = 2.5 V, fSCL = 3.4 MHz, and TA = TMIN to TMAX.
Table 4. A Version2 Y Version Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE3, 4 See the Sample Delay and Bit Trial Delay section, fIN = 10 kHz sine wave for fSCL from 1.7 MHz to 3.4 MHz fIN = 1 kHz sine wave for fSCL up to 400 kHz Signal-to-Noise and 49.5 49.5 dB Distortion (SINAD)5 Total Harmonic −65 −65 dB Distortion (THD)5 Peak Harmonic or −65 −65 dB Spurious Noise (SFDR)5 Intermodulation fa = 11 kHz, fb = 9 kHz for fSCL from 1.7 MHz to Distortion (IMD)5 3.4 MHz fa = 5.4 kHz, fb = 4.6 kHz for fSCL up to 400 kHz Second-Order Terms −83 −83 dB Third-Order Terms −75 −75 dB Channel-to-Channel −90 −90 dB fIN = 10 kHz Isolation5 Full-Power Bandwidth5 14 14 MHz @ 3 dB 1.5 1.5 MHz @ 0.1 dB DC ACCURACY3, 6 Resolution 8 8 Bits Integral Nonlinearity5 ±0.04 ±0.1 LSB Differential Nonlinearity5 ±0.05 ±0.1 LSB Guaranteed no missed codes to eight bits Offset Error5 ±0.3 ±0.5 LSB Offset Error Matching ±0.02 ±0.05 LSB Offset Temperature Drift 4.26 4.26 ppm/°C Gain Error5 ±0.06 ±0.175 LSB Gain Error Matching ±0.03 ±0.06 LSB Gain Temperature Drift 0.59 0.59 ppm/°C ANALOG INPUT Input Voltage Range 0 VREF 0 VREF V VREF = VIN3/VREF or VDD DC Leakage Current ±1 ±1 μA Input Capacitance 34 34 pF Channel 0 to Channel 2—during acquisition phase 4 4 pF Channel 0 to Channel 2—outside acquisition phase 35 35 pF Channel 3—during acquisition phase 5 5 pF Channel 3—outside acquisition phase REFERENCE INPUT VREF Input Voltage Range 1.2 VDD 1.2 VDD V DC Leakage Current ±1 ±1 μA VREF Input Capacitance 5 5 pF Outside conversion phase 35 35 pF During conversion phase Input Impedance 69 69 kΩ Rev. B | Page 7 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7991 AD7995 AD7999 I2C TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CONVERTER OPERATION ADC Transfer Function TYPICAL CONNECTION DIAGRAM ANALOG INPUT INTERNAL REGISTER STRUCTURE CONFIGURATION REGISTER SAMPLE DELAY AND BIT TRIAL DELAY CONVERSION RESULT REGISTER SERIAL INTERFACE SERIAL BUS ADDRESS WRITING TO THE AD7991/AD7995/AD7999 READING FROM THE AD7991/AD7995/AD7999 PLACING THE AD7991/AD7995/AD7999 INTO HIGH SPEED MODE MODE OF OPERATION OUTLINE DIMENSIONS ORDERING GUIDE
AD7991/AD7995/AD7999 AD79991
The temperature range for the Y version is −40°C to +125°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V, VREF = 2.5 V, fSCL = 3.4 MHz, and TA = TMIN to TMAX.
Table 4. A Version2 Y Version Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE3, 4 See the Sample Delay and Bit Trial Delay section, fIN = 10 kHz sine wave for fSCL from 1.7 MHz to 3.4 MHz fIN = 1 kHz sine wave for fSCL up to 400 kHz Signal-to-Noise and 49.5 49.5 dB Distortion (SINAD)5 Total Harmonic −65 −65 dB Distortion (THD)5 Peak Harmonic or −65 −65 dB Spurious Noise (SFDR)5 Intermodulation fa = 11 kHz, fb = 9 kHz for fSCL from 1.7 MHz to Distortion (IMD)5 3.4 MHz fa = 5.4 kHz, fb = 4.6 kHz for fSCL up to 400 kHz Second-Order Terms −83 −83 dB Third-Order Terms −75 −75 dB Channel-to-Channel −90 −90 dB fIN = 10 kHz Isolation5 Full-Power Bandwidth5 14 14 MHz @ 3 dB 1.5 1.5 MHz @ 0.1 dB DC ACCURACY3, 6 Resolution 8 8 Bits Integral Nonlinearity5 ±0.04 ±0.1 LSB Differential Nonlinearity5 ±0.05 ±0.1 LSB Guaranteed no missed codes to eight bits Offset Error5 ±0.3 ±0.5 LSB Offset Error Matching ±0.02 ±0.05 LSB Offset Temperature Drift 4.26 4.26 ppm/°C Gain Error5 ±0.06 ±0.175 LSB Gain Error Matching ±0.03 ±0.06 LSB Gain Temperature Drift 0.59 0.59 ppm/°C ANALOG INPUT Input Voltage Range 0 VREF 0 VREF V VREF = VIN3/VREF or VDD DC Leakage Current ±1 ±1 μA Input Capacitance 34 34 pF Channel 0 to Channel 2—during acquisition phase 4 4 pF Channel 0 to Channel 2—outside acquisition phase 35 35 pF Channel 3—during acquisition phase 5 5 pF Channel 3—outside acquisition phase REFERENCE INPUT VREF Input Voltage Range 1.2 VDD 1.2 VDD V DC Leakage Current ±1 ±1 μA VREF Input Capacitance 5 5 pF Outside conversion phase 35 35 pF During conversion phase Input Impedance 69 69 kΩ Rev. B | Page 7 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7991 AD7995 AD7999 I2C TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CONVERTER OPERATION ADC Transfer Function TYPICAL CONNECTION DIAGRAM ANALOG INPUT INTERNAL REGISTER STRUCTURE CONFIGURATION REGISTER SAMPLE DELAY AND BIT TRIAL DELAY CONVERSION RESULT REGISTER SERIAL INTERFACE SERIAL BUS ADDRESS WRITING TO THE AD7991/AD7995/AD7999 READING FROM THE AD7991/AD7995/AD7999 PLACING THE AD7991/AD7995/AD7999 INTO HIGH SPEED MODE MODE OF OPERATION OUTLINE DIMENSIONS ORDERING GUIDE