Datasheet AD9627 (Analog Devices) - 31

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AD9627
In some applications, it may be acceptable to drive the sample Jitter in the rising edge of the input is still of paramount concern clock inputs with a single-ended CMOS signal. In such applica- and is not easily reduced by the internal stabilization circuit. tions, the CLK+ pin should be driven directly from a CMOS gate, The duty cycle control loop does not function for clock rates and the CLK− pin should be bypassed to ground with a 0.1 μF less than 20 MHz nominally. The loop has a time constant capacitor in parallel with a 39 kΩ resistor (see Figure 60). associated with it thatmust be considered where the clock rate CLK+ can be driven directly from a CMOS gate. Although the can change dynamically. A wait time of 1.5 μs to 5 μs is required CLK+ input circuit supply is AVDD (1.8 V), this input is designed after a dynamic clock frequency increase or decrease before the to withstand input voltages of up to 3.6 V, making the selection DCS loop is relocked to the input signal. During the time period of the drive logic voltage very flexible. that the loop is not locked, the DCS loop is bypassed, and internal device timing is dependent on the duty cycle of the input clock
V
signal. In such applications, it may be appropriate to disable the
CC OPTIONAL 0.1µF
duty cycle stabilizer. In all other applications, enabling the DCS
1kΩ AD951x 100Ω 0.1µF CLOCK CLK+ INPUT CMOS DRIVER
circuit is recommended to maximize ac performance.
50Ω1 1kΩ ADC AD9627 Jitter Considerations CLK–
High speed, high resolution ADCs are sensitive to the quality
0.1µF 39kΩ
0 of the clock input. The degradation in SNR from the low 06 71-
150Ω RESISTOR IS OPTIONAL.
frequency SNR (SNR 065 LF) at a given input frequency (fINPUT) due Figure 60. Single-Ended 1.8 V CMOS Sample Clock (Up to 150 MSPS) to jitter (tJRMS) can be calculated by SNR ( /10 LF SNR HF = −10 log[(2π × fINPUT × tJRMS)2 + 10 ) ]
VCC
In the equation, the rms aperture jitter represents the clock input
OPTIONAL 0.1µF 1kΩ AD951x 100Ω 0.1µF
jitter specification. IF undersampling applications are particularly
CLOCK CLK+ INPUT CMOS DRIVER
sensitive to jitter, as illustrated in Figure 62.
50Ω1 1kΩ ADC AD9627 75 0.1µF CLK–
-061
70 150Ω RESISTOR IS OPTIONAL.
6571
0.05ps
0 Figure 61. Single-Ended 3.3 V CMOS Sample Clock (Up to 150 MSPS)
MEASURED 0.20ps 65 Input Clock Divider Bc)
The AD9627 contains an input clock divider with the ability to
d 60 0.5ps R (
divide the input clock by integer values between 1 and 8. If a
N S
divide ratio other than 1 is selected, the duty cycle stabilizer is
55 1.0ps
automatically enabled.
1.50ps 50
The AD9627 clock divider can be synchronized using the external
2.00ps
SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the clock
2.50ps 3.00ps 45
divider to be resynchronized on every SYNC signal or only on
1 10 100 1000
62 0 1- the first SYNC signal after the register is written. A valid SYNC
INPUT FREQUENCY (MHz)
57 06 causes the clock divider to reset to its initial state. This synchro- Figure 62. SNR vs. Input Frequency and Jitter nization feature allows multiple parts to have their clock dividers The clock input should be treated as an analog signal in cases aligned to guarantee simultaneous input sampling. where aperture jitter may affect the dynamic range of the AD9627.
Clock Duty Cycle
Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock Typical high speed ADCs use both clock edges to generate signal with digital noise. Low jitter, crystal-controlled oscillators a variety of internal timing signals and, as a result, may be make the best clock sources. If the clock is generated from another sensitive to clock duty cycle. Commonly, a ±5% tolerance is type of source (by gating, dividing, or another method), it should required on the clock duty cycle to maintain dynamic be retimed by the original clock at the last step. performance characteristics. Refer to Application Note AN-501 and Application Note AN-756 The AD9627 contains a duty cycle stabilizer (DCS) that retimes (see www.analog.com) for more information about jitter perform- the nonsampling (falling) edge, providing an internal clock ance as it relates to ADCs. signal with a nominal 50% duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD9627. Noise and distortion performance are nearly flat for a wide range of duty cycles with the DCS on, as shown in Figure 43. Rev. B | Page 30 of 76 Document Outline Features Applications Functional Block Diagram Product Highlights Revision History General Description Specifications ADC DC Specifications—AD9627-80/AD9627-105 ADC DC Specifications—AD9627-125/AD9627-150 ADC AC Specifications—AD9627-80/AD9627-105 ADC AC Specifications—AD9627-125/AD9627-150 Digital Specifications Switching Specifications—AD9627-80/AD9627-105 Switching Specifications—AD9627-125/AD9627-150 Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configurations and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Single-Ended Input Configuration Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) ADC Overrange and Gain Control Fast Detect Overview ADC Fast Magnitude ADC Overrange (OR) Gain Switching Coarse Upper Threshold (C_UT) Fine Upper Threshold (F_UT) Fine Lower Threshold (F_LT) Increment Gain (IG) and Decrement Gain (DG) Signal Monitor Peak Detector Mode RMS/MS Magnitude Mode Threshold Crossing Mode Additional Control Bits Signal Monitor Enable Bit Complex Power Calculation Mode Enable Bit DC Correction DC Correction Bandwidth DC Correction Readback DC Correction Freeze DC Correction Enable Bits Signal Monitor SPORT Output SMI SCLK SMI SDFS SMI SDO Built-In Self-Test (BIST) and Output Test Built-In Self-Test (BIST) Output Test Modes Channel/Chip Synchronization Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Sync Control (Register 0x100) Bit 7—Signal Monitor Sync Enable Bits[6:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable Fast Detect Control (Register 0x104) Bits[7:4]—Reserved Bits[3:1]—Fast Detect Mode Select Bit 0—Fast Detect Enable Coarse Upper Threshold (Register 0x105) Bits[7:3]—Reserved Bits[2:0]—Coarse Upper Threshold Fine Upper Threshold (Register 0x106 and Register 0x107) Register 0x106, Bits[7:0]—Fine Upper Threshold[7:0] Register 0x107, Bits[7:5]—Reserved Register 0x107, Bits[4:0]—Fine Upper Threshold[12:8] Fine Lower Threshold (Register 0x108 and Register 0x109) Register 0x108, Bits[7:0]—Fine Lower Threshold[7:0] Register 0x109, Bits[7:5]—Reserved Register 0x109, Bits[4:0]—Fine Lower Threshold[12:8] Increase Gain Dwell Time (Register 0x10A and Register 0x10B) Register 0x10A, Bits[7:0]—Increase Gain Dwell Time[7:0] Register 0x10B, Bits[7:0]—Increase Gain Dwell Time[15:8] Signal Monitor DC Correction Control (Register 0x10C) Bit 7—Reserved Bit 6—DC Correction Freeze Bits[5:2]—DC Correction Bandwidth Bit 1—DC Correction for Signal Path Enable Bit 0—DC Correction for Signal Monitor Enable Signal Monitor DC Value Channel A (Register 0x10D and Register 0x10E) Register 0x10D, Bits[7:0]—DC Value Channel A[7:0] Register 0x10E, Bits[7:6]—Reserved Register 0x10E, Bits[5:0]—DC Value Channel A[13:8] Signal Monitor DC Value Channel B (Register 0x10F and Register 0x110) Register 0x10F, Bits[7:0]—DC Value Channel B[7:0] Register 0x110, Bits[7:6]—Reserved Register 0x110, Bits[5:0]—DC Value Channel B[13:8] Signal Monitor SPORT Control (Register 0x111) Bit 7—Reserved Bit 6—RMS/MS Magnitude Output Enable Bit 5—Peak Detector Output Enable Bit 4—Threshold Crossing Output Enable Bits[3:2]—SPORT SMI SCLK Divide Bit 1— SPORT SMI SCLK Sleep Bit 0—Signal Monitor SPORT Output Enable Signal Monitor Control (Register 0x112) Bit 7—Complex Power Calculation Mode Enable Bits[6:4]—Reserved Bit 3—Signal Monitor RMS/MS Select Bits[2:1]—Signal Monitor Mode Bit 0—Signal Monitor Enable Signal Monitor Period (Register 0x113 to Register 0x115) Register 0x113, Bits[7:0]—Signal Monitor Period[7:0] Register 0x114, Bits[7:0]—Signal Monitor Period[15:8] Register 0x115, Bits[7:0]—Signal Monitor Period[23:16] Signal Monitor Result Channel A (Register 0x116 to Register 0x118) Register 0x116, Bits[7:0]—Signal Monitor Result Channel A[7:0] Register 0x117, Bits[7:0]—Signal Monitor Result Channel A[15:8] Register 0x118, Bits[7:4]—Reserved Register 0x118, Bits[3:0]—Signal Monitor Result Channel A[19:16] Signal Monitor Result Channel B (Register 0x119 to Register 0x11B) Register 0x119, Bits[7:0]— Signal Monitor Result Channel B[7:0] Register 0x11A, Bits[7:0]—Signal Monitor Result Channel B[15:8] Register 0x11B, Bits[7:4]—Reserved Register 0x11B, Bits[3:0]—Signal Monitor Result Channel B[19:16] Applications Information Design Guidelines Power and Ground Recommendations LVDS Operation Exposed Paddle Thermal Heat Slug Recommendations CML RBIAS Reference Decoupling SPI Port Evaluation Board Power Supplies Input Signals Output Signals Default Operation and Jumper Selection Settings POWER VIN CLOCK PDWN CSB SCLK/DFS SDIO/DCS Alternative Clock Configurations Alternative Analog Input Drive Configuration Schematics Evaluation Board Layouts Bill of Materials Outline Dimensions Ordering Guide