Datasheet AD9626 (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | 12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter |
| 页数 / 页 | 37 / 5 — AD9626. AC SPECIFICATIONS. Table 2. AD9626-170. AD9626-210. AD9626-250. … |
| 文件格式/大小 | PDF / 1.4 Mb |
| 文件语言 | 英语 |
AD9626. AC SPECIFICATIONS. Table 2. AD9626-170. AD9626-210. AD9626-250. Parameter2. Temp. Min. Typ. Max. Unit
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AD9626 AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, Single Port Output mode, DCS enabled, unless otherwise noted.1
Table 2. AD9626-170 AD9626-210 AD9626-250 Parameter2 Temp Min Typ Max Min Typ Max Min Typ Max Unit
SNR fIN = 10 MHz 25°C 64.5 64.4 64.0 dB Full 63.6 63.0 dB fIN = 70 MHz 25°C 64.4 64.2 63.8 dB Full 63.0 62.3 dB SINAD fIN = 10 MHz 25°C 64.5 64.4 64.0 dB Full 63.5 62.8 dB fIN = 70 MHz 25°C 64.2 64.0 63.4 dB Full 62.6 62.0 dB EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz 25°C 10.6 10.6 10.5 Bits fIN = 70 MHz 25°C 10.5 10.5 10.5 Bits WORST HARMONIC (SECOND OR THIRD) fIN = 10 MHz 25°C 84 86 83 dBc Full 75 77 73 dBc fIN = 70 MHz 25°C 79 79 80 dBc Full 71 73 71 dBc WORST OTHER (SFDR EXCLUDING SECOND AND THIRD) fIN = 10 MHz 25°C 92 90 84 dBc Full 85 79 76 dBc fIN = 70 MHz 25°C 92 87 84 dBc Full 81 77 73 dBc TWO-TONE IMD 140.2 MHz/141.3 MHz @ −7 dBFS 25°C 80 dBFS 170.2 MHz/171.3 MHz @ −7 dBFS 25°C 83 83 dBc ANALOG INPUT BANDWIDTH 25°C 700 700 700 MHz 1 All ac specifications tested by driving CLK+ and CLK− differentially. 2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Rev. 0 | Page 4 of 36 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Out-of-Range TIMING—SINGLE PORT MODE TIMING—INTERLEAVED MODE fS/2 Spurious LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS Exposed Paddle Thermal Heat Slug Recommendations CML RBIAS AD9626 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
AD9626 AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, Single Port Output mode, DCS enabled, unless otherwise noted.1
Table 2. AD9626-170 AD9626-210 AD9626-250 Parameter2 Temp Min Typ Max Min Typ Max Min Typ Max Unit
SNR fIN = 10 MHz 25°C 64.5 64.4 64.0 dB Full 63.6 63.0 dB fIN = 70 MHz 25°C 64.4 64.2 63.8 dB Full 63.0 62.3 dB SINAD fIN = 10 MHz 25°C 64.5 64.4 64.0 dB Full 63.5 62.8 dB fIN = 70 MHz 25°C 64.2 64.0 63.4 dB Full 62.6 62.0 dB EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz 25°C 10.6 10.6 10.5 Bits fIN = 70 MHz 25°C 10.5 10.5 10.5 Bits WORST HARMONIC (SECOND OR THIRD) fIN = 10 MHz 25°C 84 86 83 dBc Full 75 77 73 dBc fIN = 70 MHz 25°C 79 79 80 dBc Full 71 73 71 dBc WORST OTHER (SFDR EXCLUDING SECOND AND THIRD) fIN = 10 MHz 25°C 92 90 84 dBc Full 85 79 76 dBc fIN = 70 MHz 25°C 92 87 84 dBc Full 81 77 73 dBc TWO-TONE IMD 140.2 MHz/141.3 MHz @ −7 dBFS 25°C 80 dBFS 170.2 MHz/171.3 MHz @ −7 dBFS 25°C 83 83 dBc ANALOG INPUT BANDWIDTH 25°C 700 700 700 MHz 1 All ac specifications tested by driving CLK+ and CLK− differentially. 2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Rev. 0 | Page 4 of 36 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Out-of-Range TIMING—SINGLE PORT MODE TIMING—INTERLEAVED MODE fS/2 Spurious LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS Exposed Paddle Thermal Heat Slug Recommendations CML RBIAS AD9626 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE