Datasheet AD9601 (Analog Devices) - 4
| 制造商 | Analog Devices |
| 描述 | 10-Bit, 200 MSPS/250 MSPS 1.8 V Analog-to-Digital Converter |
| 页数 / 页 | 33 / 4 — AD9601. SPECIFICATIONS DC SPECIFICATIONS. Table 1. AD9601-200. … |
| 文件格式/大小 | PDF / 989 Kb |
| 文件语言 | 英语 |
AD9601. SPECIFICATIONS DC SPECIFICATIONS. Table 1. AD9601-200. AD9601-250. Parameter1. Temp. Min. Typ. Max. Unit
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AD9601 SPECIFICATIONS DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, single port output mode, DCS enabled, unless otherwise noted.
Table 1. AD9601-200 AD9601-250 Parameter1 Temp Min Typ Max Min Typ Max Unit
RESOLUTION 10 10 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error 25°C 4.0 4.0 mV Full −12 +12 −12 +12 mV Gain Error 25°C 1.4 1.4 % FS Full −2.1 +4.5 −2.1 +4.5 % FS Differential Nonlinearity (DNL) 25°C 0.2 0.2 LSB Full −0.5 +0.5 −0.5 +0.5 LSB Integral Nonlinearity (INL) 25°C 0.2 0.2 LSB Full −0.5 +0.5 −0.5 +0.5 LSB TEMPERATURE DRIFT Offset Error Full 8 8 μV/°C Gain Error Full 0.021 0.021 %/°C ANALOG INPUTS (VIN+, VIN−) Differential Input Voltage Range2 Full 0.98 1.25 1.5 0.98 1.25 1.5 V p-p Input Common-Mode Voltage Full 1.4 1.4 V Input Resistance (Differential) Full 4.3 4.3 kΩ Input Capacitance 25°C 2 2 pF POWER SUPPLY AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Currents I 3 AVDD Full 133 142 157 167 mA I 3 DRVDD /Single Port Mode4 Full 19 20 22 24 mA I 3 DRVDD /Interleaved Mode5 Full 16 18 mA Power Dissipation3 Full mW Single Port Mode4 Full 274 291 322 344 mW Interleaved Mode5 Full 268 315 mW Power-Down Mode Supply Currents IAVDD Full 40 40 μA IDRVDD Full 170 170 22 μA Standby Mode Supply Currents IAVDD Full 19 19 mA IDRVDD Full 170 170 22 μA 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section. 3 IAVDD and IDRVDD are measured with a −1 dBFS, 10.3 MHz sine input at rated sample rate. 4 Single data rate mode; this is the default mode of the AD9601. 5 Interleaved mode; user-programmable feature. See the Memory Map section. Rev. 0 | Page 3 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Out-of-Range TIMING—SINGLE PORT MODE TIMING—INTERLEAVED MODE fS/2 Spurious LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS Exposed Paddle Thermal Heat Slug Recommendations CML RBIAS AD9601 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
AD9601 SPECIFICATIONS DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, single port output mode, DCS enabled, unless otherwise noted.
Table 1. AD9601-200 AD9601-250 Parameter1 Temp Min Typ Max Min Typ Max Unit
RESOLUTION 10 10 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error 25°C 4.0 4.0 mV Full −12 +12 −12 +12 mV Gain Error 25°C 1.4 1.4 % FS Full −2.1 +4.5 −2.1 +4.5 % FS Differential Nonlinearity (DNL) 25°C 0.2 0.2 LSB Full −0.5 +0.5 −0.5 +0.5 LSB Integral Nonlinearity (INL) 25°C 0.2 0.2 LSB Full −0.5 +0.5 −0.5 +0.5 LSB TEMPERATURE DRIFT Offset Error Full 8 8 μV/°C Gain Error Full 0.021 0.021 %/°C ANALOG INPUTS (VIN+, VIN−) Differential Input Voltage Range2 Full 0.98 1.25 1.5 0.98 1.25 1.5 V p-p Input Common-Mode Voltage Full 1.4 1.4 V Input Resistance (Differential) Full 4.3 4.3 kΩ Input Capacitance 25°C 2 2 pF POWER SUPPLY AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Currents I 3 AVDD Full 133 142 157 167 mA I 3 DRVDD /Single Port Mode4 Full 19 20 22 24 mA I 3 DRVDD /Interleaved Mode5 Full 16 18 mA Power Dissipation3 Full mW Single Port Mode4 Full 274 291 322 344 mW Interleaved Mode5 Full 268 315 mW Power-Down Mode Supply Currents IAVDD Full 40 40 μA IDRVDD Full 170 170 22 μA Standby Mode Supply Currents IAVDD Full 19 19 mA IDRVDD Full 170 170 22 μA 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section. 3 IAVDD and IDRVDD are measured with a −1 dBFS, 10.3 MHz sine input at rated sample rate. 4 Single data rate mode; this is the default mode of the AD9601. 5 Interleaved mode; user-programmable feature. See the Memory Map section. Rev. 0 | Page 3 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Out-of-Range TIMING—SINGLE PORT MODE TIMING—INTERLEAVED MODE fS/2 Spurious LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS Exposed Paddle Thermal Heat Slug Recommendations CML RBIAS AD9601 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE