Datasheet AD9600 (Analog Devices)

10-Bit, 105 MSPS/125 MSPS/150 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9600 FEATURES I/Q demodulation systems SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS Smart antenna systems SFDR = 81 dBc to 70 MHz at 150 MSPS Digital predistortion Low power: 825 mW at 150 MSPS General-purpose software radios 1.8 V analog supply operation Broadband data applications 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply Data acquisition Integer 1 to 8 input clock divider Nondestructive testing Intermediate frequency (IF) sampling frequencies up to 450 MHz PRODUCT HIGHLIGHTS Internal analog-to-digital converter (ADC) voltage reference
1. Integrated dual, 10-bit, 150 MSPS/125 MSPS/105 MSPS ADC.
Integrated ADC sample-and-hold inputs
2. Fast overrange detect and signal monitor with serial output.
Flexible analog input: 1 V p-p to 2 V p-p range
3. Signal monitor block with dedicated serial output mode.
Differential analog inputs with 650 MHz bandwidth
4. Proprietary differential input maintains excellent SNR
ADC clock duty cycle stabilizer
performance for input frequencies up to 450 MHz.
95 dB channel isolation/crosstalk
5. The AD9600 operates from a single 1.8 V supply and
Serial port control
features a separate digital output driver supply to
User-configurable built-in self-test (BIST) capability
accommodate 1.8 V to 3.3 V logic families.
Energy-saving power-down modes
6. A standard serial port interface supports various product
Integrated receive features
features and functions, such as data formatting (offset
Fast detect/threshold bits
binary, twos complement, or gray coding), enabling the
Composite signal monitor
clock DCS, power-down mode, and voltage reference mode.
APPLICATIONS
7. The AD9600 is pin compatible with the AD9627-11, AD9627,
Point-to-point radio receivers (GPSK, QAM)
and AD9640, allowing a simple migration from 10 bits to
Diversity radio systems
11 bits, 12 bits, or 14 bits.
FUNCTIONAL BLOCK DIAGRAM SDIO/ SCLK/ AVDD DVDD FD[0:3]A DCS DFS CSB DRVDD R FD BITS/THRESHOLD SPI AD9600 DETECT FE DS F V U D9A /L S T B O U VIN + A PROGRAMMING DATA D0A CM TP SHA ADC U O VIN – A CLK+ VREF – + DIVIDE 1 TO 8 CLK– SENSE SIGNAL MONITOR DCOA CML REFERENCE DUTY CYCLE DCO SELECT STABLIZER GENERATION DCOB R VIN – B E SHA ADC F DS F D9B SERIAL MONITOR V VIN + B DATA /L BU S O UT P D0B CM MULTICHIP FD BITS/THRESHOLD SERIAL MONITOR UT O SYNC DETECT INTERFACE AGND SYNC FD[0:3]B SMI SMI SMI DRGND SDFS SCLK/ SDO/ PDWN OEB
1
NOTES
-00
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
09
SEE FIGURE 7 FOR LVDS PIN NAMES.
69 0 Figure 1.
Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved.
Document Outline FEATURES APPLICATIONS PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) ADC OVERRANGE AND GAIN CONTROL FAST DETECT OVERVIEW ADC FAST MAGNITUDE ADC OVERRANGE (OR) GAIN SWITCHING Coarse Upper Threshold (C_UT) Fine Upper Threshold (F_UT) Fine Lower Threshold (F_LT) Increment Gain (IG) and Decrement Gain (DG) SIGNAL MONITOR PEAK DETECTOR MODE RMS/MS MAGNITUDE MODE THRESHOLD CROSSING MODE ADDITIONAL CONTROL BITS Signal Monitor Enable Bit Complex Power Calculation Mode Enable Bit DC CORRECTION DC Correction Bandwidth DC Correction Readback DC Correction Freeze DC Correction Enable Bits SIGNAL MONITOR SPORT OUTPUT SMI SCLK SMI SDFS SMI SDO BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES CHANNEL/CHIP SYNCHRONIZATION SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP TABLE Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP MEMORY MAP REGISTER DESCRIPTION Sync Control (Register 0x100) Bit 7—Signal Monitor Sync Enable Bits [6:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable Fast Detect Control (Register 0x104) Bits [7:4]—Reserved Bits [3:1]—Fast Detect Mode Select Bit 0—Fast Detect Enable Coarse Upper Threshold (Register 0x105) Bits [7:3]—Reserved Bits [2:0]—Coarse Upper Threshold Fine Upper Threshold (Register 0x106 and Register 0x107) Register 0x106, Bits [7:0]—Fine Upper Threshold [7:0] Register 0x107, Bits [7:5]—Reserved Register 0x107, Bits [4:0]—Fine Upper Threshold [12:8] Fine Lower Threshold (Register 0x108 and Register 0x109) Register 0x108, Bits [7:0]—Fine Lower Threshold [7:0]Register 0x109, Bits [7:5]—ReservedRegister 0x109, Bits [4:0]—Fine Lower Threshold [12:8] Increase Gain Dwell Time (Register 0x10A andRegister 0x10B) Register 0x10A, Bits [7:0]—Increase Gain Dwell Time [7:0]Register 0x10B, Bits [7:0]—Increase Gain Dwell Time [15:8] Signal Monitor DC Correction Control (Register 0x10C) Bit 7—ReservedBit 6—DC Correction Freeze Bits [5:2]—DC Correction Bandwidth Bit 1—DC Correction for Signal Path Enable Bit 0—DC Correction for Signal Monitor Enable Signal Monitor DC Value Channel A (Register 0x10D and Register 0x10E) Register 0x10D, Bits [7:0]—DC Value Channel A [7:0] Register 0x10E, Bits [7:6]—Reserved Register 0x10E, Bits [5:0]—DC Value Channel A [13:8] Signal Monitor DC Value Channel B (Register 0x10F and Register 0x110) Register 0x10F Bits [7:0]—DC Value Channel B [7:0] Register 0x110 Bits [7:6]—Reserved Register 0x110 Bits [5:0]—DC Value Channel B [13:8] Signal Monitor SPORT Control (Register 0x111) Bit 7—Reserved Bit 6—RMS/MS Magnitude Output Enable Bit 5—Peak Detector Output Enable Bit 4—Threshold Crossing Output Enable Bits [3:2]—SPORT SMI SCLK Divide Bit 1— SPORT SMI SCLK Sleep Bit 0—Signal Monitor SPORT Output Enable Signal Monitor Control (Register 0x112) Bit 7—Complex Power Calculation Mode Enable Bits [6:4]—Reserved Bit 3—Signal Monitor RMS/MS Select Bits [2:1]—Signal Monitor Mode Bit 0—Signal Monitor Enable Signal Monitor Period (Register 0x113 to Register 0x115) Register 0x113, Bits [7:0]—Signal Monitor Period [7:0] Register 0x114, Bits [7:0]—Signal Monitor Period [15:8] Register 0x115, Bits [7:0]—Signal Monitor Period [23:16] Signal Monitor Result Channel A (Register 0x116 to Register 0x118) Register 0x116, Bits [7:0]—Signal Monitor Result Channel A [7:0] Register 0x117, Bits [7:0]—Signal Monitor Result Channel A [15:8] Register 0x118, Bits [7:4]—Reserved Register 0x118, Bits [3:0]—Signal Monitor Result Channel A [19:16] Signal Monitor Result Channel B (Register 0x119 to Register 0x11B) Register 0x119, Bits [7:0]— Signal Monitor Result Channel B [7:0] Register 0x11A, Bits [7:0]—Signal Monitor Result Channel B [15:8] Register 0x11B, Bits [7:4]—Reserved Register 0x11B, Bits [3:0]—Signal Monitor Result Channel B [19:16] APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations CML RBIAS Reference Decoupling SPI Port EVALUATION BOARD POWER SUPPLIES INPUT SIGNALS OUTPUT SIGNALS DEFAULT OPERATION AND JUMPER SELECTION SETTINGS POWER VIN RBIAS CLOCK PDWN CSB SCLK/DFS SDIO/DCS ALTERNATIVE CLOCK CONFIGURATIONS ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION SCHEMATICS EVALUATION BOARD LAYOUTS BILL OF MATERIALS OUTLINE DIMENSIONS ORDERING GUIDE