Datasheet AD7984 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | 18-Bit, 1.33 MSPS PulSAR 10.5 mW ADC in MSOP/QFN |
| 页数 / 页 | 25 / 6 — Data Sheet. AD7984. TIMING SPECIFICATIONS. Table 4. Parameter. Symbol. … |
| 修订版 | B |
| 文件格式/大小 | PDF / 667 Kb |
| 文件语言 | 英语 |
Data Sheet. AD7984. TIMING SPECIFICATIONS. Table 4. Parameter. Symbol. Min. Typ. Max. Unit. 500µA. Y% VIO1. X% VIO1. tDELAY. TO SDO. 1.4V. VIH. 20pF
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Data Sheet AD7984 TIMING SPECIFICATIONS
TA = −40°C to +85°C, VDD = 2.37 V to 2.63 V, VIO = 2.3 V to 5.5 V, unless otherwise noted.1
Table 4. Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available tCONV 300 500 ns Acquisition Time tACQ 250 ns Time Between Conversions tCYC 750 ns CNV Pulse Width (CS Mode) tCNVH 10 ns SCK Period (CS Mode) tSCK VIO Above 4.5 V 10.5 ns VIO Above 3 V 12 ns VIO Above 2.7 V 13 ns VIO Above 2.3 V 15 ns SCK Period (Chain Mode) tSCK VIO Above 4.5 V 11.5 ns VIO Above 3 V 13 ns VIO Above 2.7 V 14 ns VIO Above 2.3 V 16 ns SCK Low Time tSCKL 4.5 ns SCK High Time tSCKH 4.5 ns SCK Falling Edge to Data Remains Valid tHSDO 3 ns SCK Falling Edge to Data Valid Delay tDSDO VIO Above 4.5 V 9.5 ns VIO Above 3 V 11 ns VIO Above 2.7 V 12 ns VIO Above 2.3 V 14 ns CNV or SDI Low to SDO D15 MSB Valid (CS Mode) tEN VIO Above 3 V 10 ns VIO Above 2.3 V 15 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 20 ns SDI Valid Setup Time from CNV Rising Edge tSSDICNV 5 ns SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 2 ns SDI Valid Hold Time from CNV Rising Edge (Chain Mode) tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 5 ns SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 2 ns SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 3 ns SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI 15 ns 1 See Figure 2 and Figure 3 for load conditions.
500µA I Y% VIO1 OL X% VIO1 tDELAY tDELAY 2 2 V TO SDO 1.4V IH VIH 2 2 C V V L IL IL 20pF 1FOR VIO ≤ 3.0V, X = 90, AND Y = 10; FOR VIO > 3.0V, X = 70, AND Y = 30.
002
500µA I 2MINIMUM V
003
OH IH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS SPECIFICATIONS IN TABLE 3.
06973- 06973- Figure 2. Load Circuit for Digital Interface Timing Figure 3. Voltage Levels for Timing Rev. B | Page 5 of 24 Document Outline FEATURES APPLICATIONS APPLICATION DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION Transfer Functions TYPICAL CONNECTION DIAGRAM ANALOG INPUTS DRIVER AMPLIFIER CHOICE SINGLE-TO-DIFFERENTIAL DRIVER VOLTAGE REFERENCE INPUT POWER SUPPLY DIGITAL INTERFACE MODE, 3-CS WIRE WITHOUT BUSY INDICATOR CS MODE, 3-WIRE WITH BUSY INDICATOR CS MODE, 4-WIRE WITHOUT BUSY INDICATOR CS MODE, 4-WIRE WITH BUSY INDICATOR CHAIN MODE WITHOUT BUSY INDICATOR CHAIN MODE WITH BUSY INDICATOR APPLICATION HINTS LAYOUT EVALUATING THE AD7984 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD7984 TIMING SPECIFICATIONS
TA = −40°C to +85°C, VDD = 2.37 V to 2.63 V, VIO = 2.3 V to 5.5 V, unless otherwise noted.1
Table 4. Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available tCONV 300 500 ns Acquisition Time tACQ 250 ns Time Between Conversions tCYC 750 ns CNV Pulse Width (CS Mode) tCNVH 10 ns SCK Period (CS Mode) tSCK VIO Above 4.5 V 10.5 ns VIO Above 3 V 12 ns VIO Above 2.7 V 13 ns VIO Above 2.3 V 15 ns SCK Period (Chain Mode) tSCK VIO Above 4.5 V 11.5 ns VIO Above 3 V 13 ns VIO Above 2.7 V 14 ns VIO Above 2.3 V 16 ns SCK Low Time tSCKL 4.5 ns SCK High Time tSCKH 4.5 ns SCK Falling Edge to Data Remains Valid tHSDO 3 ns SCK Falling Edge to Data Valid Delay tDSDO VIO Above 4.5 V 9.5 ns VIO Above 3 V 11 ns VIO Above 2.7 V 12 ns VIO Above 2.3 V 14 ns CNV or SDI Low to SDO D15 MSB Valid (CS Mode) tEN VIO Above 3 V 10 ns VIO Above 2.3 V 15 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 20 ns SDI Valid Setup Time from CNV Rising Edge tSSDICNV 5 ns SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 2 ns SDI Valid Hold Time from CNV Rising Edge (Chain Mode) tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 5 ns SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 2 ns SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 3 ns SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI 15 ns 1 See Figure 2 and Figure 3 for load conditions.
500µA I Y% VIO1 OL X% VIO1 tDELAY tDELAY 2 2 V TO SDO 1.4V IH VIH 2 2 C V V L IL IL 20pF 1FOR VIO ≤ 3.0V, X = 90, AND Y = 10; FOR VIO > 3.0V, X = 70, AND Y = 30.
002
500µA I 2MINIMUM V
003
OH IH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS SPECIFICATIONS IN TABLE 3.
06973- 06973- Figure 2. Load Circuit for Digital Interface Timing Figure 3. Voltage Levels for Timing Rev. B | Page 5 of 24 Document Outline FEATURES APPLICATIONS APPLICATION DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION Transfer Functions TYPICAL CONNECTION DIAGRAM ANALOG INPUTS DRIVER AMPLIFIER CHOICE SINGLE-TO-DIFFERENTIAL DRIVER VOLTAGE REFERENCE INPUT POWER SUPPLY DIGITAL INTERFACE MODE, 3-CS WIRE WITHOUT BUSY INDICATOR CS MODE, 3-WIRE WITH BUSY INDICATOR CS MODE, 4-WIRE WITHOUT BUSY INDICATOR CS MODE, 4-WIRE WITH BUSY INDICATOR CHAIN MODE WITHOUT BUSY INDICATOR CHAIN MODE WITH BUSY INDICATOR APPLICATION HINTS LAYOUT EVALUATING THE AD7984 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE