Datasheet AD7764 (Analog Devices) - 9

AD7764 Data Sheet ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a
Table 4.
stress rating only; functional operation of the product at these
Parameter Rating
or any other conditions above those indicated in the operational AVDD1 to Ground −0.3 V to +2.8 V section of this specification is not implied. Operation beyond AVDD2, AVDD3, AVDD4 to Ground −0.3 V to +6 V the maximum operating conditions for extended periods may DVDD to Ground −0.3 V to +2.8 V affect product reliability. VINA+, VINA− to Ground1 −0.3 V to +6 V
ESD CAUTION
VIN+, VIN− to Ground1 −0.3 V to +6 V Digital Input Voltage to Ground2 −0.3 V to +2.8 V VREF+ to Ground3 −0.3 V to +6 V AGND to DGND −0.3 V to +0.3 V Input Current to Any Pin Except Supplies4 ±10 mA Operating Temperature Range, Commercial −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance (1s0p)5 143°C/W θJA Thermal Impedance (2s2p)6, 7 71.1°C/W θJC Thermal Impedance8 20°C/W Solder Reflow Temperature9 260°C ESD 1 kV 1 The absolute maximum voltage for VIN−, VIN+, VINA−, and VINA+ is 6.0 V or AVDD3 + 0.3 V, whichever is lower. 2 The absolute maximum voltage on the digital input is 3.0 V or DVDD + 0.3 V, whichever is lower. 3 The absolute maximum voltage on the VREF+ input is 6.0 V or AVDD4 + 0.3 V, whichever is lower. 4 Transient currents of up to 100 mA do not cause SCR latch-up. 5 1s0p means a single-layer printed circuit board (PCB), which includes one signal layer and zero power layers. 6 2s2p means a 4-layer PCB, which includes 2 signal layers and 2 power layers. 7 θJA for a 2s2p PCB is derived from simulation. 8 The revised θJC (thermal impedance) is derived from simulation. 9 Maximum reflow temperature as per JEDEC J-SDT-020. Rev. B | Page 8 of 33 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION Σ-Δ MODULATION AND DIGITAL FILTERING AD7764 ANTIALIAS PROTECTION INPUT STRUCTURE ON-CHIP DIFFERENTIAL AMPLIFIER MODULATOR INPUT STRUCTURE DRIVING THE MODULATOR INPUTS DIRECTLY AD7764 SERIAL INTERFACE READING DATA READING STATUS AND OTHER REGISTERS WRITING TO THE AD7764 FUNCTIONALITY SYNCHRONIZATION OVERRANGE ALERTS POWER MODES Low Power Mode RESETB/PWRDWNB Mode DECIMATION RATE PIN DAISY-CHAINING READING DATA IN DAISY-CHAIN MODE WRITING DATA IN DAISY-CHAIN MODE CLOCKING THE AD7764 MCLK JITTER REQUIREMENTS Example 1 Example 2 DECOUPLING AND LAYOUT INFORMATION SUPPLY DECOUPLING REFERENCE VOLTAGE FILTERING DIFFERENTIAL AMPLIFIER COMPONENTS LAYOUT CONSIDERATIONS USING THE AD7764 BIAS RESISTOR SELECTION AD7764 REGISTERS CONTROL REGISTER STATUS REGISTER GAIN REGISTER—ADDRESS 0x0004 Nonbit Mapped, Default Value: 0xA000 OVERRANGE REGISTER—ADDRESS 0x0005 Nonbit Mapped, Default Value: 0xCCCC OUTLINE DIMENSIONS ORDERING GUIDE