Datasheet AD7366-5, AD7367-5 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | True Bipolar Input, 14-Bit, 2-Channel, Simultaneous Sampling SAR ADC |
| 页数 / 页 | 28 / 7 — AD7366-5/AD7367-5. TIMING SPECIFICATIONS. Table 4. Parameter 2.7. VDRIVE … |
| 修订版 | B |
| 文件格式/大小 | PDF / 460 Kb |
| 文件语言 | 英语 |
AD7366-5/AD7367-5. TIMING SPECIFICATIONS. Table 4. Parameter 2.7. VDRIVE ≤ 5.25 V. Unit. Test Conditions/Comments
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AD7366-5/AD7367-5 TIMING SPECIFICATIONS
AVCC = DVCC = 4.75 V to 5.25 V; VDD = 5 V to 16.5 V; VSS = −16.5 V to −5 V; VDRIVE = 2.7 V to 5.25 V; TA = TMIN to TMAX, unless otherwise noted.1
Table 4. Parameter 2.7 V ≤ VDRIVE ≤ 5.25 V Unit Test Conditions/Comments
tCONVERT Conversion time, internal clock. CONVST falling edge to BUSY falling edge. 1.25 μs max For the AD7367-5. 1.25 μs max For the AD7366-5. f SCLK 10 kHz min Frequency of serial read clock. 20 MHz max tQUIET 50 ns min Minimum quiet time required between the end of serial read and the start of the next conversion. t1 10 ns min Minimum CONVST low pulse. t2 40 ns min CONVST falling edge to BUSY rising edge. t3 0 ns min BUSY falling edge to MSB valid once CS is low for t4 prior to BUSY going low. t4 10 ns max Delay from CS falling edge until Pin 1 (DOUTA) and Pin 23 (DOUTB) are three-state disabled. t 2 5 20 ns max Data access time after SCLK falling edge. t6 7 ns min SCLK to data valid hold time. t7 0.3 × tSCLK ns min SCLK low pulse width. t8 0.3 × tSCLK ns min SCLK high pulse width. t9 10 ns max CS rising edge to DOUTA, DOUTB, high impedance. tPOWER-UP 70 μs max Power up time from shutdown mode; time required between CONVST rising edge and CONVST falling edge. 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V. All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the Terminology section and Figure 25. 2 The time required for the output to cross is 0.4 V or 2.4 V. Rev. B | Page 7 of 28 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7366-5 SPECIFICATIONS AD7367-5 SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ANALOG INPUTS TRANSFER FUNCTION Track-and-Hold TYPICAL CONNECTION DIAGRAM DRIVER AMPLIFIER CHOICE VDRIVE REFERENCE MODES OF OPERATION NORMAL MODE SHUTDOWN MODE POWER-UP TIMES SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7366-5/AD7367-5 TO ADSP-218x AD7366-5/AD7367-5 TO ADSP-BF53x AD7366-5/AD7367-5 TO TMS320VC5506 AD7366-5/AD7367-5 TO DSP563xx APPLICATION HINTS LAYOUT AND GROUNDING EVALUATING THE AD7366-5/AD7367-5 OUTLINE DIMENSIONS ORDERING GUIDE
AD7366-5/AD7367-5 TIMING SPECIFICATIONS
AVCC = DVCC = 4.75 V to 5.25 V; VDD = 5 V to 16.5 V; VSS = −16.5 V to −5 V; VDRIVE = 2.7 V to 5.25 V; TA = TMIN to TMAX, unless otherwise noted.1
Table 4. Parameter 2.7 V ≤ VDRIVE ≤ 5.25 V Unit Test Conditions/Comments
tCONVERT Conversion time, internal clock. CONVST falling edge to BUSY falling edge. 1.25 μs max For the AD7367-5. 1.25 μs max For the AD7366-5. f SCLK 10 kHz min Frequency of serial read clock. 20 MHz max tQUIET 50 ns min Minimum quiet time required between the end of serial read and the start of the next conversion. t1 10 ns min Minimum CONVST low pulse. t2 40 ns min CONVST falling edge to BUSY rising edge. t3 0 ns min BUSY falling edge to MSB valid once CS is low for t4 prior to BUSY going low. t4 10 ns max Delay from CS falling edge until Pin 1 (DOUTA) and Pin 23 (DOUTB) are three-state disabled. t 2 5 20 ns max Data access time after SCLK falling edge. t6 7 ns min SCLK to data valid hold time. t7 0.3 × tSCLK ns min SCLK low pulse width. t8 0.3 × tSCLK ns min SCLK high pulse width. t9 10 ns max CS rising edge to DOUTA, DOUTB, high impedance. tPOWER-UP 70 μs max Power up time from shutdown mode; time required between CONVST rising edge and CONVST falling edge. 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V. All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the Terminology section and Figure 25. 2 The time required for the output to cross is 0.4 V or 2.4 V. Rev. B | Page 7 of 28 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7366-5 SPECIFICATIONS AD7367-5 SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ANALOG INPUTS TRANSFER FUNCTION Track-and-Hold TYPICAL CONNECTION DIAGRAM DRIVER AMPLIFIER CHOICE VDRIVE REFERENCE MODES OF OPERATION NORMAL MODE SHUTDOWN MODE POWER-UP TIMES SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7366-5/AD7367-5 TO ADSP-218x AD7366-5/AD7367-5 TO ADSP-BF53x AD7366-5/AD7367-5 TO TMS320VC5506 AD7366-5/AD7367-5 TO DSP563xx APPLICATION HINTS LAYOUT AND GROUNDING EVALUATING THE AD7366-5/AD7367-5 OUTLINE DIMENSIONS ORDERING GUIDE