Datasheet AD7366, AD7367 (Analog Devices) - 9

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AD7366/AD7367 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DOUTA 1 24 DGND V 2 23 D DRIVE OUTB DV 3 22 CC BUSY RANGE1 4 AD7366/ 21 CNVST RANGE0 AD7367 5 20 SCLK ADDR TOP VIEW 6 19 CS (Not to Scale) AGND 7 18 REFSEL AV 8 17 AGND CC D 9 16 CAPA DCAPB VSS 10 15 VDD V 11 14 A1 VB1
002
V 12 13 A2 VB2
06703- Figure 2. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Description
1, 23 D A, D B Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on OUT OUT the falling edge of the SCLK input; 12 SCLK cycles are required to access a result from the AD7366, and 14 SCLK cycles are required for the AD7367. The data simultaneously appears on both pins from the simultaneous con- versions of both ADCs. The data stream consists of the 12 bits of conversion data for the AD7366 and 14 bits for the AD7367 and is provided MSB first. If CS is held low for a further 14 SCLK cycles, on either D A or D B, the OUT OUT data from the other ADC follows on that D pin. Note, the second serial result from the AD7366 is preceeded OUT by two zeros. Therfore data from a simultaneous conversion on both ADCs can be gathered in serial format on either D A or D B using only one serial port. See the Serial Interface section for more information. OUT OUT 2 V Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates. DRIVE This pin should be decoupled to DGND. The voltage range on this pin is 2.7 V to 5.25 V and may be different from the voltage at AV and DV , but should never exceed either by more than 0.3 V. To achieve a throughput CC CC rate of 1.12 MSPS for the AD7366 or 1 MSPS for the AD7367, V must be ≥ 4.75 V. DRIVE 3 DV Digital Supply Voltage, 4.75 V to 5.25 V. The DV and AV voltages should ideally be at the same potential. CC CC CC For best performance, it is recommended that the DV and AV pins be shorted together, to ensure that the CC CC voltage difference between them never exceeds 0.3 V even on a transient basis. This supply should be decoupled to DGND. Place 10 µF and 100 nF decoupling capacitors on the DV pin. CC 4, 5 RANGE1, Analog Input Range Selection, Logic Inputs. The polarity on these pins determines the input range of the analog RANGE0 input channels. See the Analog Inputs section and Table 8 for details. 6 ADDR Multiplexer Select, Logic Input. This input is used to select the pair of channels to be simultaneously converted, either Channel 1 of both ADC A and ADC B, or Channel 2 of both ADC A and ADC B. The logic state on this pin is latched on the rising edge of BUSY to set up the multiplexer for the next conversion. 7, 17 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7366/AD7367. All analog input signals and any external reference signal should be referred to this AGND voltage. Both AGND pins should connect to the AGND plane of a system. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 8 AV Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the ADC cores. The AV and DV voltages CC CC CC should ideally be at the same potential. For best performance, it is recommended that the DV and AV pins be CC CC shorted together, to ensure that the voltage difference between them never exceeds 0.3 V even on a transient basis. This supply should be decoupled to AGND. Place 10 µF and 100 nF decoupling capacitors on the AV pin. CC 9, 16 D A, D B Decoupling Capacitor Pins. Decoupling capacitors are connected to these pins to decouple the reference buffer CAP CAP for each respective ADC. For best performance, it is recommended that a 680 nF decoupling capacitor be used on these pins. Provided the output is buffered, the on-chip reference can be taken from these pins and applied externally to the rest of a system. 10 V Negative Power Supply Voltage. This is the negative supply voltage for the high voltage analog input structure SS of the AD7366/AD7367. The supply must be less than a maximum voltage of −11.5 V for all analog input ranges. See Table 7 for more details. Place 10 µF and 100 nF decoupling capacitors on the V pin. SS 11, 12 V , V Analog Inputs of ADC A. Both analog inputs are single-ended. The analog input range on these channels is A1 A2 determined by the RANGE0 and RANGE1 pins. 13, 14 V , V Analog Inputs of ADC B. Both analog inputs are single-ended. The analog input range on these channels is B2 B1 determined by the RANGE0 and RANGE1 pins. 15 V Positive Power Supply Voltage. This is the positive supply voltage for the high voltage analog input structure of DD the AD7366/AD7367. The supply must be greater than a minimum voltage of 11.5 V for all analog input ranges. See Table 7 for more details. Place 10 µF and 100 nF decoupling capacitors on the V pin. DD Rev. D | Page 9 of 28 Document Outline Features Functional Block Diagram General Description Product Highlights Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Circuit Information Converter Operation Analog Inputs Transfer Function Track-and-Hold Typical Connection Diagram Driver Amplifier Choice VDRIVE Reference Modes of Operation Normal Mode Shutdown Mode Power-Up Times Serial Interface Microprocessor Interfacing AD7366/AD7367 to ADSP-218x AD7366/AD7367 to ADSP-BF53x AD7366/AD7367 to TMS320VC5506 AD7366/AD7367 to DSP563xx Application Hints Layout and Grounding Outline Dimensions Ordering Guide