Datasheet AD9211 (Analog Devices) - 4
| 制造商 | Analog Devices |
| 描述 | 10-Bit, 200 MSPS/250 MSPS/300 MSPS, 1.8 V Analog-to-Digital Converter |
| 页数 / 页 | 29 / 4 — AD9211. SPECIFICATIONS DC SPECIFICATIONS. Table 1. AD9211-200. … |
| 文件格式/大小 | PDF / 1.3 Mb |
| 文件语言 | 英语 |
AD9211. SPECIFICATIONS DC SPECIFICATIONS. Table 1. AD9211-200. AD9211-250. AD9211-300. Parameter. Temp
该数据表的模型线
文件文字版本
link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 26 link to page 26
AD9211 SPECIFICATIONS DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.
Table 1. AD9211-200 AD9211-250 AD9211-300 Parameter
1
Temp Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION 10 10 10 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error 25°C 4.3 4.6 4.4 mV Full −12 +12 −13 +13 −13 +13 mV Gain Error 25°C 1.0 1.3 1.1 % FS Full −2.2 +4.3 −2.2 +4.3 −2.2 +4.3 % FS Differential Nonlinearity (DNL) 25°C ±0.1 ±0.1 ±0.1 LSB Full −0.5 +0.5 −0.5 +0.5 −0.5 +0.5 LSB Integral Nonlinearity (INL) 25°C ±0.2 ±0.2 ±0.2 LSB Full −0.35 0.35 −0.45 0.45 −0.7 +0.7 LSB TEMPERATURE DRIFT Offset Error Full ±8 ±7 ±6 μV/°C Gain Error Full 0.018 0.018 0.018 %/°C ANALOG INPUTS (VIN+, VIN−) Differential Input Voltage Range2 Full 0.98 1.25 1.5 0.98 1.25 1.5 0.98 1.25 1.5 V p-p Input Common-Mode Voltage Full 1.4 1.4 1.4 V Input Resistance (Differential) Full 4.3 4.3 4.3 kΩ Input Capacitance 25°C 2 2 2 pF POWER SUPPLY AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Currents I 3 AVDD Full 134 144 158 169 189 203 mA I 3 DRVDD /SDR Mode4 Full 51 54 53 55 54 57 mA I 3 DRVDD /DDR Mode5 Full 35 38 39 mA Power Dissipation3 Full mW SDR Mode4 Full 333 356 380 403 437 468 mW DDR Mode5 Full 304 353 410 mW 1 See the AN-835 application note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section. 3 IAVDD and IDRVDD are measured with a −1 dBFS, 10.3 MHz sine input at rated sample rate. 4 Single data rate mode; this is the default mode of the AD9211. 5 Double data rate mode; user-programmable feature. See the Memory Map section. Rev. 0 | Page 3 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING RBIAS AD9211 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE
AD9211 SPECIFICATIONS DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.
Table 1. AD9211-200 AD9211-250 AD9211-300 Parameter
1
Temp Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION 10 10 10 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error 25°C 4.3 4.6 4.4 mV Full −12 +12 −13 +13 −13 +13 mV Gain Error 25°C 1.0 1.3 1.1 % FS Full −2.2 +4.3 −2.2 +4.3 −2.2 +4.3 % FS Differential Nonlinearity (DNL) 25°C ±0.1 ±0.1 ±0.1 LSB Full −0.5 +0.5 −0.5 +0.5 −0.5 +0.5 LSB Integral Nonlinearity (INL) 25°C ±0.2 ±0.2 ±0.2 LSB Full −0.35 0.35 −0.45 0.45 −0.7 +0.7 LSB TEMPERATURE DRIFT Offset Error Full ±8 ±7 ±6 μV/°C Gain Error Full 0.018 0.018 0.018 %/°C ANALOG INPUTS (VIN+, VIN−) Differential Input Voltage Range2 Full 0.98 1.25 1.5 0.98 1.25 1.5 0.98 1.25 1.5 V p-p Input Common-Mode Voltage Full 1.4 1.4 1.4 V Input Resistance (Differential) Full 4.3 4.3 4.3 kΩ Input Capacitance 25°C 2 2 2 pF POWER SUPPLY AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Currents I 3 AVDD Full 134 144 158 169 189 203 mA I 3 DRVDD /SDR Mode4 Full 51 54 53 55 54 57 mA I 3 DRVDD /DDR Mode5 Full 35 38 39 mA Power Dissipation3 Full mW SDR Mode4 Full 333 356 380 403 437 468 mW DDR Mode5 Full 304 353 410 mW 1 See the AN-835 application note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section. 3 IAVDD and IDRVDD are measured with a −1 dBFS, 10.3 MHz sine input at rated sample rate. 4 Single data rate mode; this is the default mode of the AD9211. 5 Double data rate mode; user-programmable feature. See the Memory Map section. Rev. 0 | Page 3 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING RBIAS AD9211 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE