Datasheet AD7634 (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | 18-Bit, 670 kSPS, Differential Programmable Input PulSAR ADC |
| 页数 / 页 | 33 / 9 — AD7634. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. BUF. … |
| 修订版 | B |
| 文件格式/大小 | PDF / 688 Kb |
| 文件语言 | 英语 |
AD7634. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. BUF. DBUF. DRE. VEE. 48 47 46 45 44 43 42 41 40 39 38 37. AGND 1
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AD7634 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IN D F N BUF P D G F M D ND C F F DBUF DRE + – P P RE TE AV IN AG VEE VC IN RE RE 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 36 BIPOLAR AVDD PIN 1 2 35 CNVST MODE0 3 34 PD MODE1 4 33 RESET D0/OB/2C 5 32 CS AD7634 WARP 6 31 RD TOP VIEW IMPULSE 7 30 (Not to Scale) TEN D1/A0 8 29 BUSY D2/A1 9 28 D17/SCCS D3 10 27 D16/SCCLK D4/DIVSCLK[0] 11 26 D15/SCIN D5/DIVSCLK[1] 12 25 D14/HW/SW 13 14 15 16 17 18 19 20 21 22 23 24 K N D D T U K C R /INT NC L DI N D DD ND O T Y C S O X S S OG OV DV DG D DCL RR E S S 12/SYN /INV INV 0/ D6/ 11/ D RDE D7 D8/ 9/RDC/ D1 D
-004
D 3/
406
D1
06
NOTES 1. FOR THE LEAD FRAME CHIP SCALE PACKAGE (LFCSP), THE EXPOSED PAD SHOULD BE CONNECTED TO VEE. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES.
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Type1 Description
1, 42 AGND P Analog Power Ground Pins. Ground reference point for all analog I/O. All analog I/O should be refer- enced to AGND and should be connected to the analog ground plane of the system. In addition, the AGND, DGND, and OGND voltages should be at the same potential. 2, 44 AVDD P Analog Power Pins. Nominally 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. 3, 4 MODE[0:1] DI Data Input/Output Interface Mode Selection.
Interface Mode MODE1 MODE0 Description
0 Low Low 18-bit interface 1 Low High 16-bit interface 2 High Low 8-bit (byte) interface 3 High High Serial interface 5 D0/OB/2C DI/O2 In 18-bit parallel mode, this output is used as Bit 0 of the parallel port data output bus and the data coding is straight binary. In all other modes, this pin allows the choice of straight binary or twos complement. When OB/2C = high, the digital output is straight binary When OB/2C = low, the MSB is inverted resulting in a twos complement output from its internal shift register. 6 WARP DI2 Conversion Mode Selection. See the Modes of Operation section for a more detailed description. Used in conjunction with the IMPULSE input per the following:
Conversion Mode WARP IMPULSE
Normal Low Low Impulse Low High Warp High Low Normal High High 7 IMPULSE DI2 Conversion Mode Selection. See the WARP pin description in this table. See the Modes of Operation section for a more detailed description. Rev. B | Page 8 of 32 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION OVERVIEW CONVERTER OPERATION MODES OF OPERATION Warp Mode Normal Mode Impulse Mode TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS Input Range Selection Input Structure Single-to-Differential Driver VOLTAGE REFERENCE INPUT/OUTPUT Internal Reference (REF = 5 V) (PDREF = Low, PDBUF = Low) External 2.5 V Reference and Internal Buffer (REF = 5 V)(PDREF = High, PDBUF = Low) External 5 V Reference (PDREF = High, PDBUF = High) Reference Decoupling Temperature Sensor POWER SUPPLIES Core Supplies High Voltage Supplies Digital Output Supply Power Sequencing Power Dissipation vs. Throughput Power Down CONVERSION CONTROL INTERFACES DIGITAL INTERFACE RESET PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 18-Bit Interface (Master or Slave) 16-Bit and 8-Bit Interface (Master or Slave) SERIAL INTERFACE Data Interface MASTER SERIAL INTERFACE Internal Clock (MODE[1:0] = 3, EXT/ = Low) Read During Convert (RDC = High) Read After Covert (RDC = Low, DIVSCLK[1:0] = 0 to 3) SLAVE SERIAL INTERFACE External Clock (MODE[1:0] = 3, EXT/ = High) External Discontinuous Clock Data Read After Conversion Daisy-Chain Feature External Clock Data Read During Previous Conversion External Clock Data Read After/During Conversion HARDWARE CONFIGURATION SOFTWARE CONFIGURATION MICROPROCESSOR INTERFACING SPI Interface APPLICATION INFORMATION LAYOUT GUIDELINES EVALUATING PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
AD7634 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IN D F N BUF P D G F M D ND C F F DBUF DRE + – P P RE TE AV IN AG VEE VC IN RE RE 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 36 BIPOLAR AVDD PIN 1 2 35 CNVST MODE0 3 34 PD MODE1 4 33 RESET D0/OB/2C 5 32 CS AD7634 WARP 6 31 RD TOP VIEW IMPULSE 7 30 (Not to Scale) TEN D1/A0 8 29 BUSY D2/A1 9 28 D17/SCCS D3 10 27 D16/SCCLK D4/DIVSCLK[0] 11 26 D15/SCIN D5/DIVSCLK[1] 12 25 D14/HW/SW 13 14 15 16 17 18 19 20 21 22 23 24 K N D D T U K C R /INT NC L DI N D DD ND O T Y C S O X S S OG OV DV DG D DCL RR E S S 12/SYN /INV INV 0/ D6/ 11/ D RDE D7 D8/ 9/RDC/ D1 D
-004
D 3/
406
D1
06
NOTES 1. FOR THE LEAD FRAME CHIP SCALE PACKAGE (LFCSP), THE EXPOSED PAD SHOULD BE CONNECTED TO VEE. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES.
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Type1 Description
1, 42 AGND P Analog Power Ground Pins. Ground reference point for all analog I/O. All analog I/O should be refer- enced to AGND and should be connected to the analog ground plane of the system. In addition, the AGND, DGND, and OGND voltages should be at the same potential. 2, 44 AVDD P Analog Power Pins. Nominally 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. 3, 4 MODE[0:1] DI Data Input/Output Interface Mode Selection.
Interface Mode MODE1 MODE0 Description
0 Low Low 18-bit interface 1 Low High 16-bit interface 2 High Low 8-bit (byte) interface 3 High High Serial interface 5 D0/OB/2C DI/O2 In 18-bit parallel mode, this output is used as Bit 0 of the parallel port data output bus and the data coding is straight binary. In all other modes, this pin allows the choice of straight binary or twos complement. When OB/2C = high, the digital output is straight binary When OB/2C = low, the MSB is inverted resulting in a twos complement output from its internal shift register. 6 WARP DI2 Conversion Mode Selection. See the Modes of Operation section for a more detailed description. Used in conjunction with the IMPULSE input per the following:
Conversion Mode WARP IMPULSE
Normal Low Low Impulse Low High Warp High Low Normal High High 7 IMPULSE DI2 Conversion Mode Selection. See the WARP pin description in this table. See the Modes of Operation section for a more detailed description. Rev. B | Page 8 of 32 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION OVERVIEW CONVERTER OPERATION MODES OF OPERATION Warp Mode Normal Mode Impulse Mode TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS Input Range Selection Input Structure Single-to-Differential Driver VOLTAGE REFERENCE INPUT/OUTPUT Internal Reference (REF = 5 V) (PDREF = Low, PDBUF = Low) External 2.5 V Reference and Internal Buffer (REF = 5 V)(PDREF = High, PDBUF = Low) External 5 V Reference (PDREF = High, PDBUF = High) Reference Decoupling Temperature Sensor POWER SUPPLIES Core Supplies High Voltage Supplies Digital Output Supply Power Sequencing Power Dissipation vs. Throughput Power Down CONVERSION CONTROL INTERFACES DIGITAL INTERFACE RESET PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 18-Bit Interface (Master or Slave) 16-Bit and 8-Bit Interface (Master or Slave) SERIAL INTERFACE Data Interface MASTER SERIAL INTERFACE Internal Clock (MODE[1:0] = 3, EXT/ = Low) Read During Convert (RDC = High) Read After Covert (RDC = Low, DIVSCLK[1:0] = 0 to 3) SLAVE SERIAL INTERFACE External Clock (MODE[1:0] = 3, EXT/ = High) External Discontinuous Clock Data Read After Conversion Daisy-Chain Feature External Clock Data Read During Previous Conversion External Clock Data Read After/During Conversion HARDWARE CONFIGURATION SOFTWARE CONFIGURATION MICROPROCESSOR INTERFACING SPI Interface APPLICATION INFORMATION LAYOUT GUIDELINES EVALUATING PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE