Datasheet AD9254 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | 14-Bit, 150 MSPS, 1.8 V Analog-to-Digital Converter |
| 页数 / 页 | 41 / 7 — AD9254. SWITCHING SPECIFICATIONS. Table 4. AD9254BCPZ-150. Parameter. … |
| 文件格式/大小 | PDF / 1.5 Mb |
| 文件语言 | 英语 |
AD9254. SWITCHING SPECIFICATIONS. Table 4. AD9254BCPZ-150. Parameter. Temperature. Min Typ Max Unit. TIMING DIAGRAM. N + 2. N + 1. N + 3
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AD9254 SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 2.5 V, unless otherwise noted.
Table 4. AD9254BCPZ-150 Parameter
1
Temperature Min Typ Max Unit
CLOCK INPUT PARAMETERS Conversion Rate, DCS Enabled Full 20 150 MSPS Conversion Rate, DCS Disabled Full 10 150 MSPS CLK Period Full 6.7 ns CLK Pulse Width High, DCS Enabled Full 2.0 3.3 4.7 ns CLK Pulse Width High, DCS Disabled Full 3.0 3.3 3.7 ns DATA OUTPUT PARAMETERS Data Propagation Delay (tPD)2 Full 3.1 3.9 4.8 ns DCO Propagation Delay (tDCO) Full 4.4 ns Setup Time (tS) Full 1.9 2.9 ns Hold Time (tH) Full 3.0 3.8 ns Pipeline Delay (Latency) Full 12 Cycles Aperture Delay (tA) Full 0.8 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 ps rms Wake-Up Time3 Full 350 μs OUT-OF-RANGE RECOVERY TIME Full 3 Cycles SERIAL PORT INTERFACE4 SCLK Period (tCLK) Full 40 ns SCLK Pulse Width High Time (tHI) Full 16 ns SCLK Pulse Width Low Time (tLO) Full 16 ns SDIO to SCLK Setup Time (tDS) Full 5 ns SDIO to SCLK Hold Time (tDH) Full 2 ns CSB to SCLK Setup Time (tS) Full 5 ns CSB to SCLK Hold Time (tH) Full 2 ns 1 See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load. 3 Wake-up time is dependent on the value of the decoupling capacitors, values shown with 0.1 μF capacitor across REFT and REFB. 4 See Figure 50 and the Serial Port Interface (SPI) section.
TIMING DIAGRAM N + 2 N + 1 N + 3 N N + 4 N + 8 tA N + 5 N + 6 N + 7 tCLK CLK+ CLK– tPD DATA N – 13 N – 12 N – 11 N – 10 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4 tS tH tDCO tCLK
02 0
DCO
6- 21 06 Figure 2. Timing Diagram Rev. 0 | Page 6 of 40 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS DIFFERENTIAL INPUT CONFIGURATIONS VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS JITTER CONSIDERATIONS POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS TIMING SERIAL PORT INTERFACE (SPI) MEMORY MAP READING THE MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER TABLE LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS CML RBIAS REFERENCE DECOUPLING EVALUATION BOARD POWER SUPPLIES INPUT SIGNALS OUTPUT SIGNALS DEFAULT OPERATION AND JUMPER SELECTION SETTINGS ALTERNATIVE CLOCK CONFIGURATIONS ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION SCHEMATICS EVALUATION BOARD LAYOUT BILL OF MATERIALS OUTLINE DIMENSIONS ORDERING GUIDE
AD9254 SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 2.5 V, unless otherwise noted.
Table 4. AD9254BCPZ-150 Parameter
1
Temperature Min Typ Max Unit
CLOCK INPUT PARAMETERS Conversion Rate, DCS Enabled Full 20 150 MSPS Conversion Rate, DCS Disabled Full 10 150 MSPS CLK Period Full 6.7 ns CLK Pulse Width High, DCS Enabled Full 2.0 3.3 4.7 ns CLK Pulse Width High, DCS Disabled Full 3.0 3.3 3.7 ns DATA OUTPUT PARAMETERS Data Propagation Delay (tPD)2 Full 3.1 3.9 4.8 ns DCO Propagation Delay (tDCO) Full 4.4 ns Setup Time (tS) Full 1.9 2.9 ns Hold Time (tH) Full 3.0 3.8 ns Pipeline Delay (Latency) Full 12 Cycles Aperture Delay (tA) Full 0.8 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 ps rms Wake-Up Time3 Full 350 μs OUT-OF-RANGE RECOVERY TIME Full 3 Cycles SERIAL PORT INTERFACE4 SCLK Period (tCLK) Full 40 ns SCLK Pulse Width High Time (tHI) Full 16 ns SCLK Pulse Width Low Time (tLO) Full 16 ns SDIO to SCLK Setup Time (tDS) Full 5 ns SDIO to SCLK Hold Time (tDH) Full 2 ns CSB to SCLK Setup Time (tS) Full 5 ns CSB to SCLK Hold Time (tH) Full 2 ns 1 See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load. 3 Wake-up time is dependent on the value of the decoupling capacitors, values shown with 0.1 μF capacitor across REFT and REFB. 4 See Figure 50 and the Serial Port Interface (SPI) section.
TIMING DIAGRAM N + 2 N + 1 N + 3 N N + 4 N + 8 tA N + 5 N + 6 N + 7 tCLK CLK+ CLK– tPD DATA N – 13 N – 12 N – 11 N – 10 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4 tS tH tDCO tCLK
02 0
DCO
6- 21 06 Figure 2. Timing Diagram Rev. 0 | Page 6 of 40 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS DIFFERENTIAL INPUT CONFIGURATIONS VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS JITTER CONSIDERATIONS POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS TIMING SERIAL PORT INTERFACE (SPI) MEMORY MAP READING THE MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER TABLE LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS CML RBIAS REFERENCE DECOUPLING EVALUATION BOARD POWER SUPPLIES INPUT SIGNALS OUTPUT SIGNALS DEFAULT OPERATION AND JUMPER SELECTION SETTINGS ALTERNATIVE CLOCK CONFIGURATIONS ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION SCHEMATICS EVALUATION BOARD LAYOUT BILL OF MATERIALS OUTLINE DIMENSIONS ORDERING GUIDE