Datasheet AD9252 (Analog Devices)

Octal, 14-Bit, 50 MSPS, Serial LVDS, 1.8 V ADC Data Sheet AD9252 FEATURES FUNCTIONAL BLOCK DIAGRAM 8 analog-to-digital converters (ADCs) integrated into 1 package AVDD PDWN DRVDD DRGND 93.5 mW ADC power per channel at 50 MSPS AD9252 14 SNR = 73 dB (to Nyquist) VIN + A SERIAL D + A ADC ENOB = 12 bits VIN – A LVDS D – A SFDR = 84 dBc (to Nyquist) 14 VIN + B D + B SERIAL Excellent linearity ADC VIN – B LVDS D – B DNL = ±0.4 LSB (typical); INL = ±1.5 LSB (typical) 14 VIN + C SERIAL D + C Serial LVDS (ANSI-644, default) ADC VIN – C LVDS D – C Low power, reduced signal option (similar to IEEE 1596.3) 14 Data and frame clock outputs VIN + D SERIAL D + D ADC VIN – D LVDS D – D 325 MHz, full-power analog bandwidth 14 2 V p-p input voltage range VIN + E SERIAL D + E ADC VIN – E LVDS D – E 1.8 V supply operation 14 Serial port control VIN + F D + F SERIAL ADC LVDS D – F Full-chip and individual-channel power-down modes VIN – F Flexible bit orientation 14 VIN + G SERIAL D + G ADC Built-in and custom digital test pattern generation VIN – G LVDS D – G Programmable clock and data alignment 14 VIN + H SERIAL D + H Programmable output resolution ADC VIN – H LVDS D – H Standby mode VREF APPLICATIONS SENSE FCO+ 0.5V FCO– DATA RATE Medical imaging and nondestructive ultrasound REFT REF MULTIPLIER REFB SELECT SERIAL PORT DCO+ Portable ultrasound and digital beam-forming systems INTERFACE DCO– Quadrature radio receivers
001
Diversity radio receivers RBIAS AGND CSB SDIO/ SCLK/ CLK+ CLK–
96-
ODM DTP
062
Tape drives
Figure 1.
Optical networking Test equipment
The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable
GENERAL DESCRIPTION
clock and data alignment and programmable digital test pattern The AD9252 is an octal, 14-bit, 50 MSPS ADC with an on-chip generation. The available digital test patterns include built-in sample-and-hold circuit designed for low cost, low power, small size, deterministic and pseudorandom patterns, along with custom user- and ease of use. Operating at a conversion rate of up to 50 MSPS, defined test patterns entered via the serial port interface (SPI). it is optimized for outstanding dynamic performance and low The AD9252 is available in an RoHS compliant, 64-lead LFCSP. It is power in applications where a small package size is critical. specified over the industrial temperature range of −40°C to +85°C. The ADC requires a single 1.8 V power supply and LVPECL-/
PRODUCT HIGHLIGHTS
CMOS-/LVDS-compatible sample rate clock for full performance 1. Small Footprint. Eight ADCs are contained in a small package. operation. No external reference or driver components are 2. Low Power of 93.5 mW per Channel at 50 MSPS. required for many applications. 3. Ease of Use. A data clock output (DCO) operates up to The ADC automatically multiplies the sample rate clock for 350 MHz and supports double data rate (DDR) operation. the appropriate LVDS serial data rate. A data clock (DCO) 4. User Flexibility. SPI control offers a wide range of flexible for capturing data on the output and a frame clock (FCO) for features to meet specific system requirements. signaling a new output byte are provided. Individual channel 5. Pin-Compatible Family. This includes the AD9212 (10-bit) power-down is supported and typically consumes less than and AD9222 (12-bit). 2 mW when all channels are disabled.
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Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input Considerations Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/ODM Pin SCLK/DTP Pin CSB Pin RBIAS Pin Voltage Reference Internal Reference Operation External Reference Operation Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Evaluation Board Power Supplies Input Signals Output Signals Default Operation and Jumper Selection Settings Alternative Analog Input Drive Configuration Outline Dimensions Ordering Guide