Datasheet AD9212 (Analog Devices) - 4
| 制造商 | Analog Devices |
| 描述 | Octal, 10-Bit, 40 MSPS/65 MSPS, Serial LVDS, 1.8 V ADC |
| 页数 / 页 | 57 / 4 — Data Sheet. AD9212. REVISION HISTORY. 12/11—Rev. D to Rev. E. 5/10—Rev. C … |
| 修订版 | F |
| 文件格式/大小 | PDF / 1.8 Mb |
| 文件语言 | 英语 |
Data Sheet. AD9212. REVISION HISTORY. 12/11—Rev. D to Rev. E. 5/10—Rev. C to Rev. D. 12/09—Rev. B to Rev. C. 7/09—Rev. A to Rev. B
该数据表的模型线
文件文字版本
Data Sheet AD9212 REVISION HISTORY 12/11—Rev. D to Rev. E
Changes to Table 9 Endnote .. 26 Changes to Output Signals Section and Figure 70 .. 37 Changes to Digital Outputs and Timing Section .. 27 Changed Default Operation and Jumper Selection Settings Added Table 10 .. 27 Section .. 38 Changes to Table 11 and Table 12 ... 27 Added Endnote 2 in Ordering Guide ... 56 Changes to RBIAS Pin Section .. 28 Deleted Figure 63 to Figure 66 .. 28
5/10—Rev. C to Rev. D
Moved Figure 65 .. 28 Deleted LFCSP CP-64-3 Package ... Universal Changes to Serial Port Interface (SPI) Section .. 30 Changes to output_phase Register, Table 16 ... 33 Changes to Hardware Interface Section ... 30 Deleted Figure 85; Renumbered Sequentially ... 55 Changes to Table 15 .. 31 Updated Outline Dimensions .. 55 Changes to Reading the Memory Map Table Section .. 32 Changes to Ordering Guide ... 55 Added Applications Information and Design Guidelines Sections ... 35
12/09—Rev. B to Rev. C
Changes to Input Signals Section .. 36 Updated Outline Dimensions .. 55 Changes to Output Signals Section ... 36 Changes to Ordering Guide ... 56 Changes to Figure 70 .. 36 Changes to Default Operation and Jumper Selection Settings
7/09—Rev. A to Rev. B
Section .. 37 Changes to Figure 5 ... 10 Changes to Alternative Analog Input Drive Configuration Changes to Figure 49 and Figure 50 ... 21 Section .. 38 Changes to Figure 63 and Figure 64 ... 28 Changes to Figure 73 .. 38 Updated Outline Dimensions .. 55 Change to Figure 75 .. 40 Changes to Figure 76 .. 41
12/07—Rev. 0 to Rev. A
Changes to Features .. 1 Changes to Figure 80 .. 45 Changes to Figure 1 ... 1 Changes to Table 17 .. 52 Changes to Crosstalk Parameter ... 3 Updated Outline Dimensions .. 55 Changes to Logic Output (SDIO/ODM) .. 5 Changes to Ordering Guide ... 55 Changes to Figure 2 to Figure 4 ... 7
10/06—Revision 0: Initial Version
Changes to Figure 59 .. 24 Rev. E | Page 3 of 56 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input Considerations Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/ODM Pin SCLK/DTP Pin CSB Pin RBIAS Pin Voltage Reference Internal Reference Operation External Reference Operation Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Evaluation Board Power Supplies Input Signals Output Signals Default Operation and Jumper Selection Settings Alternative Analog Input Drive Configuration Outline Dimensions Ordering Guide
Changes to Table 9 Endnote .. 26 Changes to Output Signals Section and Figure 70 .. 37 Changes to Digital Outputs and Timing Section .. 27 Changed Default Operation and Jumper Selection Settings Added Table 10 .. 27 Section .. 38 Changes to Table 11 and Table 12 ... 27 Added Endnote 2 in Ordering Guide ... 56 Changes to RBIAS Pin Section .. 28 Deleted Figure 63 to Figure 66 .. 28
5/10—Rev. C to Rev. D
Moved Figure 65 .. 28 Deleted LFCSP CP-64-3 Package ... Universal Changes to Serial Port Interface (SPI) Section .. 30 Changes to output_phase Register, Table 16 ... 33 Changes to Hardware Interface Section ... 30 Deleted Figure 85; Renumbered Sequentially ... 55 Changes to Table 15 .. 31 Updated Outline Dimensions .. 55 Changes to Reading the Memory Map Table Section .. 32 Changes to Ordering Guide ... 55 Added Applications Information and Design Guidelines Sections ... 35
12/09—Rev. B to Rev. C
Changes to Input Signals Section .. 36 Updated Outline Dimensions .. 55 Changes to Output Signals Section ... 36 Changes to Ordering Guide ... 56 Changes to Figure 70 .. 36 Changes to Default Operation and Jumper Selection Settings
7/09—Rev. A to Rev. B
Section .. 37 Changes to Figure 5 ... 10 Changes to Alternative Analog Input Drive Configuration Changes to Figure 49 and Figure 50 ... 21 Section .. 38 Changes to Figure 63 and Figure 64 ... 28 Changes to Figure 73 .. 38 Updated Outline Dimensions .. 55 Change to Figure 75 .. 40 Changes to Figure 76 .. 41
12/07—Rev. 0 to Rev. A
Changes to Features .. 1 Changes to Figure 80 .. 45 Changes to Figure 1 ... 1 Changes to Table 17 .. 52 Changes to Crosstalk Parameter ... 3 Updated Outline Dimensions .. 55 Changes to Logic Output (SDIO/ODM) .. 5 Changes to Ordering Guide ... 55 Changes to Figure 2 to Figure 4 ... 7
10/06—Revision 0: Initial Version
Changes to Figure 59 .. 24 Rev. E | Page 3 of 56 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input Considerations Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/ODM Pin SCLK/DTP Pin CSB Pin RBIAS Pin Voltage Reference Internal Reference Operation External Reference Operation Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Evaluation Board Power Supplies Input Signals Output Signals Default Operation and Jumper Selection Settings Alternative Analog Input Drive Configuration Outline Dimensions Ordering Guide