Datasheet AD9259 (Analog Devices) - 4

制造商Analog Devices
描述Quad, 14-Bit, 50 MSPS Serial LVDS 1.8 V ADC
页数 / 页53 / 4 — Data Sheet. AD9259. REVISION HISTORY. 12/11—Rev. D to Rev. E. 4/10—Rev. C …
修订版E
文件格式/大小PDF / 1.7 Mb
文件语言英语

Data Sheet. AD9259. REVISION HISTORY. 12/11—Rev. D to Rev. E. 4/10—Rev. C to Rev. D. 11/09—Rev. B to Rev. C. 7/07—Rev. A to Rev. B

Data Sheet AD9259 REVISION HISTORY 12/11—Rev D to Rev E 4/10—Rev C to Rev D 11/09—Rev B to Rev C 7/07—Rev A to Rev B

该数据表的模型线

文件文字版本

Data Sheet AD9259 REVISION HISTORY 12/11—Rev. D to Rev. E
Changes to Figure 2 to Figure 4 ... 7 Changes to Output Signals Section and Figure 60 .. 35 Changes to Figure 10 ... 12 Change to Default Operation and Jumper Selection Settings Changes to Figure 15 to Figure 17, Figure 22, and Figure 31 .. 14 Section .. 36 Changes to Figure 21 and Figure 22 Captions .. 15 Change to Figure 63 .. 39 Changes to Figure 41 ... 19 Added Endnote 2 in Ordering Guide ... 51 Changes to Clock Duty Cycle Considerations Section ... 20 Changes to Power Dissipation and Power-Down Mode Section ... 21 Changes to Figure 50 to Figure 52 Captions ... 23
4/10—Rev. C to Rev. D
Change to Table 8 ... 23 Changes to Table 16 .. 33 Changes to Table 9 Endnote .. 24 Updated Outline Dimensions .. 51 Changes to Digital Outputs and Timing Section ... 25 Changes to Ordering Guide ... 51 Added Table 10 ... 25 Changes to RBIAS Pin Section .. 26 Deleted Figure 53 and Figure 54 ... 26
11/09—Rev. B to Rev. C
Changes to Figure 56 ... 27 Added EPAD Note to Figure 5 .. 11 Changes to Hardware Interface Section .. 28 Changes to Input Signals Section and Figure 60 ... 35 Added Figure 57 ... 29 Updated Outline Dimensions .. 51 Changes to Table 15 ... 29 Changes to Ordering Guide ... 51 Changes to Reading the Memory Map Table Section .. 30
7/07—Rev. A to Rev. B
Change to Output Signals Section .. 34 Change to General Description ... 1 Changes to Figure 60 ... 34 Changes to Figure 2 and Figure 4 .. 7 Changes to Default Operation and Changes to the Hardware Interface Section .. 29 Jumper Selection Settings Section ... 35 Changes to Table 17 .. 48 Changes to Alternative Analog Input Drive Configuration Section .. 36
5/07—Rev. 0 to Rev. A
Changes to Figure 63 ... 38 Changes to Effective Number of Bits (ENOB) ... 4 Changes to Table 17 ... 46 Changes to Logic Output (SDIO/ODM) .. 5 Changes to Ordering Guide ... 50 Added Endnote 3 to Table 3... 5 Change to Pipeline Latency ... 6
6/06—Revision 0: Initial Version
Rev. E | Page 3 of 52 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input Considerations Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/ODM Pin SCLK/DTP Pin CSB Pin RBIAS Pin Voltage Reference Internal Reference Operation External Reference Operation Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Evaluation Board Power Supplies Input Signals Output Signals Default Operation and Jumper Selection Settings Alternative Analog Input Drive Configuration Outline Dimensions Ordering Guide