Datasheet AD7796, AD7797 (Analog Devices) - 4

AD7796/AD7797 Data Sheet Parameter AD7796B/ AD7797B1 Unit Test Conditions/Comments
INTERNAL/EXTERNAL CLOCK Internal Clock Frequency2 64 ± 3% kHz min/max Duty Cycle 50:50 % typ External Clock Frequency 64 kHz nom A 128 kHz clock can be used if the divide by 2 function is used (Bit CLK1 = CLK0 = 1) Duty Cycle 45:55 to 55:45 % typ Applies for external 64 kHz clock (a 128 kHz clock can have a less stringent duty cycle) LOGIC INPUTS CS2 Input Low Voltage, VINL 0.8 V max DVDD = 5 V 0.4 V max DVDD = 3 V Input High Voltage, VINH 2.0 V min DVDD = 3 V or 5 V SCLK, CLK, and DIN (Schmitt-Triggered Input)2 VT(+) 1.4/2 V min/V max DVDD = 5 V VT(–) 0.8/1.7 V min/V max DVDD = 5 V VT(+) − VT(–) 0.1/0.17 V min/V max DVDD = 5 V VT(+) 0.9/2 V min/V max DVDD = 3 V VT(–) 0.4/1.35 V min/V max DVDD = 3 V VT(+) − VT(–) 0.06/0.13 V min/V max DVDD = 3 V Input Currents ±10 µA max VIN = DVDD or GND Input Capacitance 10 pF typ All digital inputs LOGIC OUTPUTS (INCLUDING CLK) Output High Voltage, V 2 OH DVDD − 0.6 V min DVDD = 3 V, ISOURCE = 100 µA 4 V min DVDD = 5 V, ISOURCE = 200 µA Output Low Voltage, V 2 OL 0.4 V max DVDD = 3 V, ISINK = 100 µA 0.4 V max DVDD = 5 V, ISINK = 1.6 mA (DOUT/RDY)/800 µA (CLK) Floating-State Leakage Current ±10 µA max Floating-State Output Capacitance 10 pF typ Data Output Coding Offset Binary SYSTEM CALIBRATION2 Full-Scale Calibration Limit +1.05 × FS V max Zero-Scale Calibration Limit −1.05 × FS V min Input Span 0.8 × FS V min 2.1 × FS V max POWER REQUIREMENTS7 Power Supply Voltage AVDD – GND 2.7/5.25 V min/max DVDD – GND 2.7/5.25 V min/max Power Supply Currents IDD Current 325 µA max 250 µA typ at AVDD = 3 V, 280 µA typ at AVDD = 5 V IDD (Power-Down Mode) 1 µA max 1 Temperature range is –40°C to +85°C. 2 Specification is not production tested, but is supported by characterization data at initial product release. 3 Following a calibration, this error is in the order of the noise for the update rate selected. 4 Recalibration at any temperature removes these errors. 5 Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (AVDD = 4 V, TA = 25°C). 6 FS[3:0] are the four bits used in the mode register to select the output word rate. 7 Digital inputs equal to DVDD or GND. Rev. B | Page 4 of 24 Document Outline FEATURES INTERFACE APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RMS NOISE AND RESOLUTION SPECIFICATIONS TYPICAL PERFORMANCE CHARACTERISTICS ON-CHIP REGISTERS COMMUNICATION REGISTER RS2, RS1, RS0 = 0, 0, 0 STATUS REGISTER RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80 MODE REGISTER RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x000A CONFIGURATION REGISTER RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x0710 DATA REGISTER RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x0000 (AD7796)/0x000000 (AD7797) ID REGISTER RS2, RS1, RS0 = 1, 0, 0; Power-On/Reset = 0x5A (AD7796)/0x5B (AD7797) OFFSET REGISTER RS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x8000 (AD7796)/0x800000 (AD7797) FULL-SCALE REGISTER RS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXX (AD7796)/0x5XXX00 (AD7797) ADC CIRCUIT INFORMATION OVERVIEW DIGITAL INTERFACE Single Conversion Mode Continuous Conversion Mode Continuous Read Mode CIRCUIT DESCRIPTION ANALOG INPUT CHANNEL BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING REFERENCE RESET BURNOUT CURRENTS AVDD MONITOR TEMPERATURE MONITOR CALIBRATION GROUNDING AND LAYOUT APPLICATIONS INFORMATION WEIGH SCALES OUTLINE DIMENSIONS ORDERING GUIDE