Datasheet AD7691 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | 18-Bit, 1.5 LSB INL, 250 kSPS PulSAR® Differential ADC in MSOP/QFN |
| 页数 / 页 | 29 / 7 — AD7691. Data Sheet. Table 5. Parameter. Symbol. Min. Typ. Max. Unit. 70% … |
| 修订版 | E |
| 文件格式/大小 | PDF / 937 Kb |
| 文件语言 | 英语 |
AD7691. Data Sheet. Table 5. Parameter. Symbol. Min. Typ. Max. Unit. 70% VIO. 500µA. IOL. 30% VIO. tDELAY. 2V OR VIO – 0.5V1. TO SDO. 1.4V
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AD7691 Data Sheet
VDD = 2.3 V to 4.5 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted.1
Table 5. Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available tCONV 0.5 3.7 µs Acquisition Time tACQ 1.8 μs Time Between Conversions tCYC 5.5 µs CNV Pulse Width (CS Mode) tCNVH 10 ns SCK Period (CS Mode) tSCK 25 ns SCK Period (Chain Mode) tSCK VIO Above 3 V 29 ns VIO Above 2.7 V 35 ns VIO Above 2.3 V 40 ns SCK Low Time tSCKL 12 ns SCK High Time tSCKH 12 ns SCK Falling Edge to Data Remains Valid tHSDO 5 ns SCK Falling Edge to Data Valid Delay tDSDO VIO Above 3 V 24 ns VIO Above 2.7 V 30 ns VIO Above 2.3 V 35 ns CNV or SDI Low to SDO D17 MSB Valid (CS Mode) tEN VIO Above 2.7 V 18 ns VIO Above 2.3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 25 ns SDI Valid Setup Time from CNV Rising Edge (CS Mode) tSSDICNV 30 ns SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 8 ns SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 8 ns SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 10 ns SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI 36 1 See Figure 3 and Figure 4 for load conditions.
70% VIO 500µA IOL 30% VIO tDELAY tDELAY 2V OR VIO – 0.5V1 2V OR VIO – 0.5V1 TO SDO 1.4V C 0.8V OR 0.5V2 0.8V OR 0.5V2 L 50pF 12V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
002
20.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
003
500µA IOH
06146- 06146- Figure 3. Load Circuit for Digital Interface Timing Figure 4. Voltage Levels for Timing Rev. E | Page 6 of 28 Document Outline FEATURES APPLICATIONS APPLICATION DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Thermal Resistance ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION Transfer Functions TYPICAL CONNECTION DIAGRAM ANALOG INPUTS DRIVER AMPLIFIER CHOICE SINGLE-TO-DIFFERENTIAL DRIVER VOLTAGE REFERENCE INPUT POWER SUPPLY SUPPLYING THE ADC FROM THE REFERENCE DIGITAL INTERFACE CS\ MODE, 3-WIRE WITHOUT BUSY INDICATOR CS\ MODE, 3-WIRE WITH BUSY INDICATOR CS\ MODE, 4-WIRE WITHOUT BUSY INDICATOR CS\ MODE, 4-WIRE WITH BUSY INDICATOR CHAIN MODE WITHOUT BUSY INDICATOR CHAIN MODE WITH BUSY INDICATOR APPLICATION HINTS LAYOUT EVALUATING THE AD7691 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
AD7691 Data Sheet
VDD = 2.3 V to 4.5 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted.1
Table 5. Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available tCONV 0.5 3.7 µs Acquisition Time tACQ 1.8 μs Time Between Conversions tCYC 5.5 µs CNV Pulse Width (CS Mode) tCNVH 10 ns SCK Period (CS Mode) tSCK 25 ns SCK Period (Chain Mode) tSCK VIO Above 3 V 29 ns VIO Above 2.7 V 35 ns VIO Above 2.3 V 40 ns SCK Low Time tSCKL 12 ns SCK High Time tSCKH 12 ns SCK Falling Edge to Data Remains Valid tHSDO 5 ns SCK Falling Edge to Data Valid Delay tDSDO VIO Above 3 V 24 ns VIO Above 2.7 V 30 ns VIO Above 2.3 V 35 ns CNV or SDI Low to SDO D17 MSB Valid (CS Mode) tEN VIO Above 2.7 V 18 ns VIO Above 2.3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 25 ns SDI Valid Setup Time from CNV Rising Edge (CS Mode) tSSDICNV 30 ns SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 8 ns SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 8 ns SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 10 ns SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI 36 1 See Figure 3 and Figure 4 for load conditions.
70% VIO 500µA IOL 30% VIO tDELAY tDELAY 2V OR VIO – 0.5V1 2V OR VIO – 0.5V1 TO SDO 1.4V C 0.8V OR 0.5V2 0.8V OR 0.5V2 L 50pF 12V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
002
20.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
003
500µA IOH
06146- 06146- Figure 3. Load Circuit for Digital Interface Timing Figure 4. Voltage Levels for Timing Rev. E | Page 6 of 28 Document Outline FEATURES APPLICATIONS APPLICATION DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Thermal Resistance ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION Transfer Functions TYPICAL CONNECTION DIAGRAM ANALOG INPUTS DRIVER AMPLIFIER CHOICE SINGLE-TO-DIFFERENTIAL DRIVER VOLTAGE REFERENCE INPUT POWER SUPPLY SUPPLYING THE ADC FROM THE REFERENCE DIGITAL INTERFACE CS\ MODE, 3-WIRE WITHOUT BUSY INDICATOR CS\ MODE, 3-WIRE WITH BUSY INDICATOR CS\ MODE, 4-WIRE WITHOUT BUSY INDICATOR CS\ MODE, 4-WIRE WITH BUSY INDICATOR CHAIN MODE WITHOUT BUSY INDICATOR CHAIN MODE WITH BUSY INDICATOR APPLICATION HINTS LAYOUT EVALUATING THE AD7691 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE