Datasheet AD7622 (Analog Devices) - 9

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AD7622 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IN ND EF BUF P D G BUF R F M D ND ND F F D + – P PD RE TE AV IN AG AG NC IN RE RE 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 36 AGND PIN 1 AVDD 2 IDENTIFIER 35 CNVST DGND 3 34 PD BYTESWAP 4 33 RESET OB/2C 5 32 CS WARP 6 AD7622 31 RD TOP VIEW NORMAL 7 30 (Not to Scale) DGND SER/PAR 8 29 BUSY D0 9 28 D15 D1 10 27 D14 D2/DIVSCLK[0] 11 26 D13 D3/DIVSCLK[1] 12 25 D12 13 14 15 16 17 18 19 20 21 22 23 24 NC = NO CONNECT T C K IN D D K R /IN N L D D DD ND UT NC O T Y C S CL Y R X S S OV DV DO S S V V OGN DG S R IN D9/
04
4/E RDC/
0
D 5/IN D8/ D10/ RDE
3-
D D6/
02
D7/ 11/
06
D
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Type
1
Description
1, 36, AGND P Analog Power Ground. 41, 42 2, 44 AVDD P Input Analog Power Pins. Nominally 2.5 V. 3 DGND P Digital Power Ground. 4 BYTESWAP DI Parallel Mode Selection (8-Bit/16-Bit). When high, the LSB is output on D[15:8] and the MSB is output on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8]. 5 OB/2C DI Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary; when low, the MSB is inverted resulting in a twos complement output from its internal shift register. 6 WARP DI Conversion Mode Selection. When WARP = high and NORMAL = high, this selects wideband warp mode with slightly improved linearity and THD. When WARP = high and NORMAL = low, this selects warp mode. In either mode, these are the fastest modes; maximum throughput is achievable, and a minimum conversion rate must be applied to guarantee full specified accuracy. 7 NORMAL DI Conversion Mode Selection. When NORMAL = low and WARP = low, this input selects normal mode where full accuracy is maintained independent of the minimum conversion rate. 8 SER/PAR DI/O Serial/Parallel Selection Input. When SER/PAR = high, the serial interface is selected and some bits of the data bus are used as a serial port; the remaining data bits are high impedance outputs. When SER/PAR = low, the parallel port is selected. 9, 10 D[0:1] DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. These pins are always outputs, regardless of the interface mode. 11, 12 D[2:3] DI/O When SER/PAR = low, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus. or DIVSCLK[0:1] When SER/PAR = high, serial clock division selection. When using serial master read after convert mode (EXT/INT = low, RDC/SDIN = low), these inputs can be used to slow down the internally generated serial clock that clocks the data output. In other serial modes, these pins are high impedance outputs. 13 D4 DI/O When SER/PAR = low, this output is used as Bit 4 of the parallel port data output bus. or EXT/INT When SER/PAR = high, serial clock source select. This input is used to select the internally generated (master) or external (slave) serial data clock. When EXT/INT = low, master mode. The internal serial clock is selected on SCLK output. When EXT/INT = high, slave mode. The output data is synchronized to an external clock signal, gated by CS, connected to the SCLK input. Rev. 0 | Page 8 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION TIMING SPECIFICATIONS PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION CIRCUIT INFORMATION CONVERTER OPERATION MODES OF OPERATION TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS MULTIPLEXED INPUTS DRIVER AMPLIFIER CHOICE Single-to-Differential Driver VOLTAGE REFERENCE INPUT Internal Reference (PDBUF = Low, PDREF = Low) External 1.2 V Reference and Internal Buffer (PDBUF = Low, PDREF = High) External 2.5 V Reference (PDBUF = High, PDREF = High) Reference Decoupling Temperature Sensor POWER SUPPLY Power Sequencing Power-Up CONVERSION CONTROL INTERFACES DIGITAL INTERFACE RESET PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 8-Bit Interface (Master or Slave) SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read After Conversion External Clock Data Read During Previous Conversion MICROPROCESSOR INTERFACING SPI Interface (ADSP-219x) APPLICATION HINTS LAYOUT EVALUATING THE AD7622 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE