Datasheet AD9461 (Analog Devices) - 8

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AD9461 ABSOLUTE MAXIMUM RATINGS Table 5. THERMAL RESISTANCE Parameter Rating
The heat sink of the AD9461 package must be soldered to ELECTRICAL ground. AVDD1 to AGND −0.3 V to +4 V AVDD2 to AGND −0.3 V to +6 V Airflow increases heat dissipation, effectively reducing θJA. Also, DRVDD to DGND −0.3 V to +4 V more metal directly in contact with the package leads from AGND to DGND −0.3 V to +0.3 V metal traces through holes, ground, and power planes reduces AVDD1 to DRVDD −4 V to +4 V the θJA. It is required that the exposed heat sink be soldered to AVDD2 to DRVDD −4 V to +6 V the ground plane. AVDD2 to AVDD −4 V to +6 V
Table 6.
D0± through D15± to DGND −0.3 V to DRVDD + 0.3 V
Package Type θ 1 2 3 JA θJB θJC Unit
CLK+/CLK− to AGND –0.3 V to AVDD1 + 0.3 V 100-Lead TQFP_EP 19.8 8.3 2 °C/W OUTPUT MODE, DCS MODE, and –0.3 V to AVDD1 + 0.3 V DFS to AGND 1 Typical θJA = 19.8°C/W (heat sink soldered) for multilayer board in still air. VIN+, VIN− to AGND −0.3 V to AVDD2 + 0.3 V 2 Typical θJB = 8.3°C/W (heat sink soldered) for multilayer board in still air. 3 VREF to AGND −0.3 V to AVDD1 + 0.3 V Typical θJC = 2°C/W (junction to exposed heat sink) represents the thermal resistance through heat sink path. SENSE to AGND −0.3 V to AVDD1 + 0.3 V REFT, REFB to AGND −0.3 V to AVDD1 + 0.3 V ENVIRONMENTAL Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C Lead Temperature (Soldering 10 sec) 300°C Junction Temperature 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 7 of 28 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW Internal Reference Connection Internal Reference Trim External Reference Operation Analog Inputs CLOCK INPUT CONSIDERATIONS Jitter Considerations POWER CONSIDERATIONS DIGITAL OUTPUTS LVDS Mode CMOS Mode TIMING OPERATIONAL MODE SELECTION Data Format Select Output Mode Select Duty Cycle Stabilizer SFDR Enhancement EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE