Datasheet AD9246 (Analog Devices) - 7

AD9246 DIGITAL SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled, unless otherwise noted.
Table 3. AD9246BCPZ-80/105/125 Parameter Temp Min Typ Max Unit
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 1.2 V Differential Input Voltage Full 0.2 6 V p-p Input Voltage Range Full AVDD − 0.3 AVDD + 1.6 V Input Common-Mode Range Full 1.1 AVDD V High Level Input Voltage (VIH) Full 1.2 3.6 V Low Level Input Voltage (VIL) Full 0 0.8 V High Level Input Current (IIH) Full −10 +10 μA Low Level Input Current (IIL) Full −10 +10 μA Input Resistance Full 8 10 12 kΩ Input Capacitance Full 4 pF LOGIC INPUTS (SCLK/DFS, OEB, PWDN) High Level Input Voltage (VIH) Full 1.2 3.6 V Low Level Input Voltage (VIL) Full 0 0.8 V High Level Input Current (IIH) Full −50 −75 μA Low Level Input Current (IIL) Full −10 +10 μA Input Resistance Full 30 kΩ Input Capacitance Full 2 pF LOGIC INPUTS (CSB) High Level Input Voltage (VIH) Full 1.2 3.6 V Low Level Input Voltage (VIL) Full 0 0.8 V High Level Input Current (IIH) Full −10 +10 μA Low Level Input Current (IIL) Full +40 +135 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF LOGIC INPUTS (SDIO/DCS) High Level Input Voltage (VIH) Full 1.2 DRVDD + 0.3 V Low Level Input Voltage (VIL) Full 0 0.8 V High Level Input Current (IIH) Full −10 +10 μA Low Level Input Current (IIL) Full +40 +130 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF DIGITAL OUTPUTS DRVDD = 3.3 V High Level Output Voltage (VOH, IOH = 50 μA) Full 3.29 V High Level Output Voltage (VOH , IOH = 0.5 mA) Full 3.25 V Low Level Output Voltage (VOL, IOL = 1.6 mA) Full 0.2 V Low Level Output Voltage (VOL, IOL = 50 μA) Full 0.05 V DRVDD = 1.8 V High Level Output Voltage (VOH, IOH = 50 μA) Full 1.79 V High Level Output Voltage (VOH, IOH = 0.5 mA) Full 1.75 V Low Level Output Voltage (VOL, IOL = 1.6 mA) Full 0.2 V Low Level Output Voltage (VOL, IOL = 50 μA) Full 0.05 V Rev. A | Page 6 of 44 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS JITTER CONSIDERATIONS POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS TIMING SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER TABLE LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS CML RBIAS REFERENCE DECOUPLING EVALUATION BOARD POWER SUPPLIES INPUT SIGNALS OUTPUT SIGNALS DEFAULT OPERATION AND JUMPER SELECTION SETTINGS ALTERNATIVE CLOCK CONFIGURATIONS ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION SCHEMATICS EVALUATION BOARD LAYOUTS BILL OF MATERIALS OUTLINE DIMENSIONS ORDERING GUIDE