Datasheet AD9246 (Analog Devices) - 9

AD9246 ABSOLUTE MAXIMUM RATINGS Table 5.
Stresses above those listed under Absolute Maximum Ratings
Parameter Rating
may cause permanent damage to the device. This is a stress ELECTRICAL rating only; functional operation of the device at these or any AVDD to AGND −0.3 V to +2.0 V other conditions above those indicated in the operational DRVDD to DGND −0.3 V to +3.9 V section of this specification is not implied. Exposure to absolute AGND to DGND −0.3 V to +0.3 V maximum rating conditions for extended periods may affect AVDD to DRVDD −3.9 V to +2.0 V device reliability. D0 through D13 to DGND −0.3 V to DRVDD + 0.3 V DCO to DGND −0.3 V to DRVDD + 0.3 V
THERMAL RESISTANCE
OR to DGND −0.3 V to DRVDD + 0.3 V The exposed paddle must be soldered to the ground plane for CLK+ to AGND −0.3 V to +3.9 V the LFCSP_VQ package. Soldering the exposed paddle to the CLK− to AGND −0.3 V to +3.9 V customer board increases the reliability of the solder joints, VIN+ to AGND −0.3 V to AVDD + 0.2 V maximizing the thermal capability of the package. VIN− to AGND −0.3 V to AVDD + 0.2 V
Table 6. Thermal Resistance
VREF to AGND −0.3 V to AVDD + 0.2 V
Package Type θJA θJC Unit
SENSE to AGND −0.3 V to AVDD + 0.2 V 48-lead LFCSP_VQ (CP-48-3) 26.4 2.4 °C/W REFT to AGND −0.3 V to AVDD + 0.2 V REFB to AGND −0.3 V to AVDD + 0.2 V Typical θJA and θJC are specified for a 4-layer board in still air. SDIO/DCS to DGND −0.3 V to DRVDD + 0.3 V Airflow increases heat dissipation effectively reducing θJA. In PDWN to AGND −0.3 V to +3.9 V addition, metal in direct contact with the package leads from CSB to AGND −0.3 V to +3.9 V metal traces, and through holes, ground, and power planes, SCLK/DFS to AGND −0.3 V to +3.9 V reduces the θJA. OEB to AGND −0.3 V to +3.9 V ENVIRONMENTAL Storage Temperature Range –65°C to +125°C Operating Temperature Range –40°C to +85°C Lead Temperature +300°C (Soldering 10 Sec) Junction Temperature +150°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 8 of 44 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS JITTER CONSIDERATIONS POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS TIMING SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER TABLE LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS CML RBIAS REFERENCE DECOUPLING EVALUATION BOARD POWER SUPPLIES INPUT SIGNALS OUTPUT SIGNALS DEFAULT OPERATION AND JUMPER SELECTION SETTINGS ALTERNATIVE CLOCK CONFIGURATIONS ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION SCHEMATICS EVALUATION BOARD LAYOUTS BILL OF MATERIALS OUTLINE DIMENSIONS ORDERING GUIDE