Datasheet AD7641 (Analog Devices) - 4

link to page 5 link to page 5 link to page 5 link to page 5 link to page 5 link to page 5 link to page 5 link to page 5
AD7641 SPECIFICATIONS
AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2. Parameter Conditions Min Typ Max Unit
RESOLUTION 18 Bits ANALOG INPUT Voltage Range VIN+ − VIN− −VREF +VREF V Operating Input Voltage VIN+, VIN− to AGND −0.1 AVDD1 V Analog Input CMRR fIN = 100 kHz 58 dB Input Current 2 MSPS throughput 18 μA Input Impedance2 THROUGHPUT SPEED Complete Cycle Wideband warp, warp modes 500 ns Throughput Rate Wideband warp, warp modes 0.001 2 MSPS Time Between Conversions Wideband warp, warp modes 1 ms Complete Cycle Normal mode 667 ns Throughput Rate Normal mode 0 1.5 MSPS DC ACCURACY Integral Linearity Error3 TMIN to TMAX = −40°C to +70°C −3 ±2 +3 LSB4 Integral Linearity Error TMIN to TMAX = −40°C to +85°C −3.5 ±2 +3.5 LSB4 No Missing Codes 18 Bits Differential Linearity Error −1 +2 LSB Transition Noise VREF = 2.5 V 1.6 LSB Transition Noise VREF = 2.048 V 2.0 LSB Zero Error, T 5 MIN to TMAX −15 +15 LSB Zero Error Temperature Drift ±0.5 ppm/°C Gain Error, T 5 MIN to TMAX −0.25 +0.25 % of FSR Gain Error Temperature Drift ±1 ppm/°C Power Supply Sensitivity AVDD = 2.5 V ± 5% ±16 LSB AC ACCURACY Dynamic Range VREF = 2.5 V 95.5 dB6 Signal-to-Noise fIN = 20 kHz, VREF = 2.5 V 93.5 dB fIN = 20 kHz, VREF = 2.048 V 92 dB fIN = 100 kHz, VREF = 2.5 V 93 dB Spurious-Free Dynamic Range fIN = 20 kHz, VREF = 2.5 V 112 dB fIN = 20 kHz, VREF = 2.048 V 113 dB fIN = 100 kHz, VREF = 2.5 V 101 dB Total Harmonic Distortion fIN = 20 kHz, VREF = 2.5 V −115 dB fIN = 20 kHz, VREF = 2.048 V −116 dB fIN = 100 kHz, VREF = 2.5 V −101 dB Signal-to-(Noise + Distortion) fIN = 20 kHz, VREF = 2.5 V 93.5 dB fIN = 20 kHz, VREF = 2.048 V 92 dB fIN = 100 kHz, VREF = 2.5 V 92.5 dB −3 dB Input Bandwidth 50 MHz SAMPLING DYNAMICS Aperture Delay 1 ns Aperture Jitter 5 ps rms Transient Response Full-scale step 115 ns INTERNAL REFERENCE PDREF = PDBUF = low Output Voltage REF @ 25°C 2.038 2.048 2.058 V Temperature Drift −40°C to +85°C ±10 ppm/°C Line Regulation AVDD = 2.5 V ± 5% ±15 ppm/V Rev. 0 | Page 3 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS APPPLICATIONS INFORMATION CIRCUIT INFORMATION CONVERTER OPERATION MODES OF OPERATION TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS MULTIPLEXED INPUTS DRIVER AMPLIFIER CHOICE Single-to-Differential Driver VOLTAGE REFERENCE INPUT Internal Reference (PDBUF = Low, PDREF = Low) External 1.2 V Reference and Internal Buffer (PDBUF = Low, PDREF = High) External 2.5 V Reference (PDBUF = High, PDREF = High) Reference Decoupling Temperature Sensor POWER SUPPLY Power Sequencing Power-Up CONVERSION CONTROL INTERFACES DIGITAL INTERFACE RESET PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 16-Bit and 8-Bit Interface (Master or Slave) SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read After Conversion External Clock Data Read During Previous Conversion MICROPROCESSOR INTERFACING SPI Interface (ADSP-219x) APPLICATION HINTS LAYOUT EVALUATING THE AD7641 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE