Datasheet AD7641 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | 18-Bit, 2 MSPS SAR ADC |
| 页数 / 页 | 29 / 7 — AD7641. Table 4. Serial Clock Timings in Master Read After Convert Mode … |
| 文件格式/大小 | PDF / 549 Kb |
| 文件语言 | 英语 |
AD7641. Table 4. Serial Clock Timings in Master Read After Convert Mode DIVSCLK[1]. 0 0 1 1. DIVSCLK[0]. Symbol. 0 1 0 1. Unit. 500µA
该数据表的模型线
文件文字版本
AD7641 Table 4. Serial Clock Timings in Master Read After Convert Mode DIVSCLK[1] 0 0 1 1 DIVSCLK[0] Symbol 0 1 0 1 Unit
SYNC to SCLK First Edge Delay Minimum t18 0.5 3 3 3 ns Internal SCLK Period Minimum t19 8 16 32 64 ns Internal SCLK Period Maximum t19 14 26 52 103 ns Internal SCLK High Minimum t20 2 6 15 31 ns Internal SCLK Low Minimum t21 3 7 16 32 ns SDOUT Valid Setup Time Minimum t22 1 5 5 5 ns SDOUT Valid Hold Time Minimum t23 0 0.5 10 28 ns SCLK Last Edge to SYNC Delay Minimum t24 0 0.5 9 26 ns BUSY High Width Maximum t24 0.630 0.870 1.350 2.28 μs
500µA IOL TO OUTPUT 1.4V PIN CL 50pF 2V 0.8V 500µA IOH tDELAY tDELAY NOTE
3
2V 2V
2
IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
00 1- 00 1-
SDOUT TIMING ARE DEFINED WITH A MAXIMUM LOAD 0.8V 0.8V
476 76 0
C
04
L OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
Figure 2. Load Circuit for Digital Interface Timing, Figure 3. Voltage Reference Levels for Timing SDOUT, SYNC, and SCLK Outputs, CL = 10 pF Rev. 0 | Page 6 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS APPPLICATIONS INFORMATION CIRCUIT INFORMATION CONVERTER OPERATION MODES OF OPERATION TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS MULTIPLEXED INPUTS DRIVER AMPLIFIER CHOICE Single-to-Differential Driver VOLTAGE REFERENCE INPUT Internal Reference (PDBUF = Low, PDREF = Low) External 1.2 V Reference and Internal Buffer (PDBUF = Low, PDREF = High) External 2.5 V Reference (PDBUF = High, PDREF = High) Reference Decoupling Temperature Sensor POWER SUPPLY Power Sequencing Power-Up CONVERSION CONTROL INTERFACES DIGITAL INTERFACE RESET PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 16-Bit and 8-Bit Interface (Master or Slave) SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read After Conversion External Clock Data Read During Previous Conversion MICROPROCESSOR INTERFACING SPI Interface (ADSP-219x) APPLICATION HINTS LAYOUT EVALUATING THE AD7641 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
SYNC to SCLK First Edge Delay Minimum t18 0.5 3 3 3 ns Internal SCLK Period Minimum t19 8 16 32 64 ns Internal SCLK Period Maximum t19 14 26 52 103 ns Internal SCLK High Minimum t20 2 6 15 31 ns Internal SCLK Low Minimum t21 3 7 16 32 ns SDOUT Valid Setup Time Minimum t22 1 5 5 5 ns SDOUT Valid Hold Time Minimum t23 0 0.5 10 28 ns SCLK Last Edge to SYNC Delay Minimum t24 0 0.5 9 26 ns BUSY High Width Maximum t24 0.630 0.870 1.350 2.28 μs
500µA IOL TO OUTPUT 1.4V PIN CL 50pF 2V 0.8V 500µA IOH tDELAY tDELAY NOTE
3
2V 2V
2
IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
00 1- 00 1-
SDOUT TIMING ARE DEFINED WITH A MAXIMUM LOAD 0.8V 0.8V
476 76 0
C
04
L OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
Figure 2. Load Circuit for Digital Interface Timing, Figure 3. Voltage Reference Levels for Timing SDOUT, SYNC, and SCLK Outputs, CL = 10 pF Rev. 0 | Page 6 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS APPPLICATIONS INFORMATION CIRCUIT INFORMATION CONVERTER OPERATION MODES OF OPERATION TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS MULTIPLEXED INPUTS DRIVER AMPLIFIER CHOICE Single-to-Differential Driver VOLTAGE REFERENCE INPUT Internal Reference (PDBUF = Low, PDREF = Low) External 1.2 V Reference and Internal Buffer (PDBUF = Low, PDREF = High) External 2.5 V Reference (PDBUF = High, PDREF = High) Reference Decoupling Temperature Sensor POWER SUPPLY Power Sequencing Power-Up CONVERSION CONTROL INTERFACES DIGITAL INTERFACE RESET PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 16-Bit and 8-Bit Interface (Master or Slave) SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read After Conversion External Clock Data Read During Previous Conversion MICROPROCESSOR INTERFACING SPI Interface (ADSP-219x) APPLICATION HINTS LAYOUT EVALUATING THE AD7641 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE