Datasheet AD7322 (Analog Devices) - 6

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Data Sheet AD7322 B Version Parameter1 Min Typ Max Unit Test Conditions/Comments
LOGIC INPUTS Input High Voltage, VINH 2.4 V Input Low Voltage, VINL 0.8 V VCC = 4.75 V to 5.25 V 0.4 V VCC = 2.7 V to 3.6 V Input Current, IIN ±1 µA VIN = 0 V or VDRIVE Input Capacitance, C 3 IN 10 pF LOGIC OUTPUTS Output High Voltage, VOH VDRIVE − 0.2 V ISOURCE = 200 µA Output Low Voltage, VOL 0.4 V ISINK = 200 µA Floating-State Leakage Current ±1 µA Floating-State Output Capacitance3 5 pF Output Coding Straight natural binary Coding bit set to 1 in control register Twos complement Coding bit set to 0 in control register CONVERSION RATE Conversion Time 800 ns 16 SCLK cycles with SCLK = 20 MHz Track-and-Hold Acquisition Time2, 3 305 ns Full-scale step input; see the Terminology section Throughput Rate 1 MSPS See the Serial Interface section; VCC = 4.75 V to 5.25 V 770 kSPS VCC < 4.75 V POWER REQUIREMENTS Digital inputs = 0 V or VDRIVE VDD 12 16.5 V See Table 6 VSS −12 −16.5 V See Table 6 VCC 2.7 5.25 V See Table 6; typical specifications for VCC < 4.75 V VDRIVE 2.7 5.25 V Normal Mode (Static) 0.9 mA VDD/VSS = ±16.5 V, VCC/VDRIVE = 5.25 V Normal Mode (Operational) fS = 1 MSPS IDD 360 µA VDD = 16.5 V ISS 410 µA VSS = −16.5 V ICC and IDRIVE 3.4 mA VCC/VDRIVE = 5.25 V Autostandby Mode (Dynamic) fS = 250 kSPS IDD 200 µA VDD = 16.5 V ISS 210 µA VSS = −16.5 V ICC and IDRIVE 1.3 mA VCC/VDRIVE = 5.25 V Autoshutdown Mode (Static) SCLK on or off IDD 1 µA VDD = 16.5 V ISS 1 µA VSS = −16.5 V ICC and IDRIVE 1 µA VCC/VDRIVE = 5.25 V Full Shutdown Mode SCLK on or off IDD 1 µA VDD = 16.5 V ISS 1 µA VSS = −16.5 V ICC and IDRIVE 1 µA VCC/VDRIVE = 5.25 V POWER DISSIPATION Normal Mode 31 mW VDD = 16.5 V, VSS = −16.5 V, VCC = 5.25 V 21 mW VDD = 12 V, VSS = −12 V, VCC = 5 V Full Shutdown Mode 38.25 µW VDD = 16.5 V, VSS = −16.5 V, VCC = 5.25 V 1 Temperature range is −40°C to +85°C. 2 See the Terminology section. 3 Sample tested during initial release to ensure compliance. 4 Unipolar 0 V to 10 V range with straight binary output coding. 5 Bipolar range with twos complement output coding. Rev. B | Page 5 of 36 Document Outline Features Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Circuit Information Converter Operation Output Coding Transfer Functions Analog Input Structure Track-and-Hold Section Typical Connection Diagram Analog Input Single-Ended Inputs True Differential Mode Pseudo Differential Inputs Driver Amplifier Choice Registers Addressing Registers Control Register Range Register Sequencer Operation Reference VDRIVE Modes of Operation Normal Mode (PM1 = PM0 = 0) Full Shutdown Mode (PM1 = PM0 = 1) Autoshutdown Mode (PM1 = 1, PM0 = 0) Autostandby Mode (PM1 = 0, PM0 = 1) Power vs. Throughput Rate Serial Interface Microprocessor Interfacing AD7322 to ADSP-21xx AD7322 to ADSP-BF53x Application Hints Layout and Grounding Power Supply Configuration Outline Dimensions Ordering Guide