Datasheet AD7762 (Analog Devices) - 9

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AD7762 Data Sheet Pin No. Mnemonic Description
10 VREF+ Reference Input. The input range of this pin is determined by the reference buffer supply voltage (AVDD4). See the Reference Voltage Filtering section for more details. 8 DECAPA Decoupling Pin. A 100 nF capacitor must be inserted between this pin and AGND1. 30 DECAPB Decoupling Pin. A 33 pF capacitor must be inserted between this pin and AGND3. 17 RBIAS Bias Current Setting Pin. A resistor must be inserted between this pin and AGND1. For more details, see the Bias Resistor Selection section. 45 to 52, DB15 to DB8 16-Bit Bidirectional Data Bus. These are three-state pins that are controlled by the CS pin and the RD/WR 54 to 61 DB7 to DB0 pin. The operating voltage for these pins is determined by the VDRIVE voltage. See the AD7762 Interface section for more details. 37 RESET A falling edge on this pin resets all internal digital circuitry and powers down the part. Holding this pin low keeps the AD7762 in a reset state. 3 MCLK Master Clock Input. A low jitter digital clock must be applied to this pin. The output data rate depends on the frequency of this clock. See the section Clocking the AD7762 for more details. 2 MCLKGND Master Clock Ground Sensing Pin. 36 SYNC Synchronization Input. A falling edge on this pin resets the internal filter. This can be used to synchronize multiple devices in a system. 39 RD/WR Read/Write Input. This pin, in conjunction with the chip select pin, is used to read and write data to and from the AD7762. If this pin is low when CS is low, a read takes place. If this pin is high and CS is low, a write occurs. See the AD7762 Interface section for more details. 38 DRDY Data Ready Output. Each time that new conversion data is available, an active low pulse, ½ ICLK period wide, is produced on this pin. See the AD7762 Interface section for more details. 40 CS Chip Select Input. Used in conjunction with the RD/WR pin to read and write data to and from the AD7762. See the AD7762 Interface section for more details. EPAD Exposed pad. Connect the exposed pad to AGNDx with six to eight vias. Rev. A | Page 8 of 28 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Terminology Typical Performance Characteristics Theory of Operation AD7762 Interface Reading Data Sharing the Parallel Bus Writing to the AD7762 Reading Status and Other Registers Clocking the AD7762 Example 1 Example 2 Driving the AD7762 Using the AD7762 Bias Resistor Selection Decoupling and Layout Recommendations Supply Decoupling Additional Decoupling Reference Voltage Filtering Differential Amplifier Components Layout Considerations Programmable FIR Filter Downloading a User-Defined Filter Example Filter Download AD7762 Registers Control Register 1—Reg 0x0001 Default Value 0x001A Control Register 2—Address 0x0002 Default Value 0x009B Status Register (Read Only) Offset Register—Address 0x0003 Non-bitmapped, Default Value 0x0000 Gain Register—Address 0x0004 Non-bitmapped, Default Value 0xA000 Overrange Register—Address 0x0005 Non-bitmapped, Default Value 0xCCCC Outline Dimensions Ordering Guide